Abstract:
A method of preparing a cathode active material having a mixed crystal is provided. The method comprises the following steps: providing a first crystalline substance having one or more members with general formulas Li xx M yy (XO 4 ) zz , LiMXO 5 , LiMXO 6 and LiMX 2 O 7 ; providing a second crystalline substance having one or more members with general formulas LiD c O 2 , Li i Ni 1-d-e Co d Mn e O 2 , LiNi 1-f-g Co f Al g O 2 , Li x Ni 1-y CoO 2 and Li m Mn 2-n E n O j and sintering the two crystalline substances to provide the mixed crystal. According to the cathode active material prepared by the method, the electrical property is superior, which enhances the duration and performance of a lithium secondary battery. Further, a method of forming a lithium ion secondary battery comprising the same is provided.
Abstract:
Described is a composite lithium compound having a mixed crystalline structure. Such compound was formed by heating a lithium compound and a metal compound together. The resulting mixed metal crystal exhibits superior electrical property and is a better cathode material for lithium secondary batteries.
Abstract:
The present invention provides a cathode active material for a lithium ion battery, and preparation method thereof. The cathode active material comprises a sintered product, the sintered product is formed by sintering lithium iron phosphate with at least one metal oxide. The metal oxide is the oxide of metals selected from a group consisting of elements of IIA, 5 IIIA, IV A, V A, IIIB, IVB, and VB. The lithium ion battery prepared from the lithium ion battery cathode active material provided in th e present invention has dramatically improved capacity.
Abstract:
A solar cell unit, a solar cell array (30), a solar cell module (100) and a manufacturing method thereof are disclosed. The solar cell unit includes a cell (31) which consists of a cell substrate (311) and a secondary grid line (312) disposed on a front surface of the cell substrate (311); a conductive wire (32) intersected and welded with the secondary grid line (312), and the secondary grid line (312) having a width in a welding position with the conductive wire (32) greater than a width thereof in a non-welding position.
Abstract:
The disclosure discloses a photovoltaic cell assembly, a photovoltaic cell array, and a solar cell assembly. The photovoltaic cell assembly includes: a plurality of photovoltaic cells arranged sequentially along a longitudinal direction, and at least one conductive band, where each photovoltaic cell includes a silicon wafer, a front conductive member disposed on a front surface of the silicon wafer, two electrodes disposed on a back surface of the silicon wafer, and a side conductive member that is disposed on a side surface of the silicon wafer and that is electrically connected between the front conductive member and one electrode, where the two electrodes extend along a transverse direction and are distributed at an interval in the longitudinal direction; and the conductive band has an extension direction the same as that of the electrode, and is electrically connected to two electrodes that are close to each other and that are respectively located on two neighboring photovoltaic cells, so that the two neighboring photovoltaic cells are connected in series or connected in parallel.
Abstract:
The disclosure discloses a photovoltaic cell, a photovoltaic cell array, a solar cell, and a method for preparing a photovoltaic cell. The photovoltaic cell includes: a silicon wafer, a gate line layer, a side electrode, a first electrode, a back electrical layer, and a second electrode. The silicon wafer includes a silicon substrate, a front diffusion layer, a side division layer, and a back division layer. At least a part of at least one of the side division layer and the back division layer is a diffusion layer whose type is the same as that of the front diffusion layer. The gate line layer is disposed on the front diffusion layer. The side electrode is disposed on the side division layer and is electrically connected to the gate line layer. The first electrode is disposed on the back division layer and is electrically connected to the side electrode. The back electrical layer and the second electrode are both disposed on a back surface of the silicon wafer. The back electrical layer is electrically connected to the second electrode and is not in contact with the first electrode.