公开(公告)号：JPH10191346A

公开(公告)日：1998-07-21

申请号：JP35104596

申请日：1996-12-27

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI

IPC: H04N19/50 ,  H04N19/423 ,  H04N19/503 ,  H04N19/51 ,  H04N19/53 ,  H04N19/57 ,  H04N19/59 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91 ,  H04N7/32

Abstract: PROBLEM TO BE SOLVED: To reduce the arithmetic amount required to calculate a motion vector by using a different evaluation function depending on the size of the grid of the retrieval area of each layer to calculate an evaluation value with respect to a notice picture element thereby detecting the motion vector. SOLUTION: A control section 2 outputs an image mode signal, a prediction mode signal, a motion vector and various control signals to control the entire system. In the case of detecting the motion vector, the control section 2 uses an evaluation function using search points of a different number depending on the size of the grid of the retrieval area of each layer in the n-step search to detect a motion. In details, wen the grid is fine, the evaluation function at sufficiently many numbers of search points is used and when the grid is rough, the evaluation function at a few numbers of search points is used to detect a motion, then the arithmetic amount required for motion detection is reduced in the n-step search.

公开(公告)号：JPH04220083A

公开(公告)日：1992-08-11

申请号：JP40412090

申请日：1990-12-20

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI

IPC: H04N1/409 ,  G06T9/00 ,  H04N1/40 ,  H04N1/41 ,  H04N1/415 ,  H04N19/117 ,  H04N19/136 ,  H04N19/14 ,  H04N19/176 ,  H04N19/196 ,  H04N19/423 ,  H04N19/60 ,  H04N19/625 ,  H04N19/86

Abstract: PURPOSE:To prevent the generation of block distortion in a low activity part, when a blocked and compressed image is recovered. CONSTITUTION:When image data is subjected to a DCT at a DCT part 3, a DC component discrimination part 11 discriminates a block including only a DC component. By a smoothing part 12 executes a smoothing processing to the block discriminated as the above-mentioned block including only the DC component to the next block at the time of recovering, the block is smoothed and block distortion is prevented.

公开(公告)号：JPH04217175A

公开(公告)日：1992-08-07

申请号：JP40375990

申请日：1990-12-19

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI ,  MATSUOKA TAKESHI

IPC: H04N1/41 ,  G06F17/14 ,  G06T1/00 ,  G06T9/00 ,  H04N1/415

Abstract: PURPOSE:To prevent the picture quality on a part with high frequency component from being deteriorated by detecting the picture edge part with the calculation of the activity of the picture information and performing DCT processing after smoothing the entire part while reducing the amplitude on this part. CONSTITUTION:A picture memory 1 stores the picture data to be encoded, the data is successively read out to be divided into 8X8 picture element blocks in a preprocessing part 2 and made into DCT in a DCT part 3. A quantization part 4 quantizes the blocks which are made into DCT by a quantization table 41, transfers the quantization data to an encoding part 5, encodes the frequency component of the quantization data and block terminal position information. In the preprocessing part 2, an activity detection part 22 detects the rise and fall of the activity. A classification part 23 separates the edge, part by the rise and fall of the activity. In an average value calculation part 24, an average value between the points with high and low activities is obtained to calculate the center of the amplitude. In an amplitude compression part 25, the amplitude is compressed to the center of this amplitude, smoothing the entire part.

公开(公告)号：JPS62244020A

公开(公告)日：1987-10-24

申请号：JP8872886

申请日：1986-04-17

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI

IPC: G02F1/133 ,  G09G3/36 ,  H04N5/66

Abstract: PURPOSE:To prevent a cobwebbing phenomenon of an image, and to improve the picture quality by deriving a difference of a gradation in one frame in a prescribed point on a liquid crystal display panel, selecting a common inversion system of a long if its difference value is large, and selecting a common inversion system of a short period if its difference value is small. CONSTITUTION:A variation detecting circuit 12 reads a digital video signal outputted from an A/D converting circuit 11, by synchronizing with a timing signal phiM from a controlling circuit 10, derives an average value of a signal level difference between each scanning line, and a variation degree of a gradation to each screen, at every screen, and outputs switching signals (a)-(d) in accordance with its variation degree. In this way, a difference of the gradation in one frame in a prescribed point on a liquid crystal display panel is derived, and if its difference value is large, a common inversion system of a long period is selected, and if the difference value is small, a common inversion system of a short period is selected, and the liquid crystal display panel is driven.

公开(公告)号：JPS62175075A

公开(公告)日：1987-07-31

申请号：JP21774386

申请日：1986-09-16

Applicant: CASIO COMPUTER CO LTD

Inventor： YAMAGISHI KOJI ,  MATSUI SHINICHI

IPC: H04N5/66

Abstract: PURPOSE:To execute sampling of all video signals in vertical direction by shifting common side data at the first and second time intervals and making a scanning electrode driving signal, sampling video data making them correspond to horizontal synchronizing signals and making a signal electrode driving signal. CONSTITUTION:A scanning electrode driving circuit 2a reads common side data SR from a display controlling section 1 in a shift register 41 in synchronism with a data shift clock phiN2 and shifts alternately at intervals of 1H and 2H. The data are sent to multiplexers 43a... through level shifters 42a... and driving signals of scanning electrodes X1... are outputted. On the other hand, signal electrode driving circuits 3a-3c selected by chip selecting signals CE1-CE3 from the display controlling section 1 takes in video data to a shift register 52 in synchronism with a clock pulse phi1 and latches in a latch circuit 53 in synchronism with a data latch clock phiN1. Then, signals luminance modulated in a luminance modulating circuit 54 are sent to multiplexer 56a... through level shifters 55a... and signal electrodes Y1, Y2... of a liquid crystal display panel 4 are driven for display.

公开(公告)号：JPS61205081A

公开(公告)日：1986-09-11

申请号：JP4603285

申请日：1985-03-08

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI ,  YAMAGISHI KOJI

IPC: H04N5/66

Abstract: PURPOSE:To secure countermeasure even to the sudden change of a video input signal and also to obtain a stable reference signal to a video input signal, by providing an independent A/D converter to supply an output of this converter to an A/D converter for video signals in the form of a reference voltage after controlling properly said output in response to the video signal. CONSTITUTION:The video signal sent from a video amplifier circuit via signal line DL is supplied to an A/D converter 1 for video signals as well as to an A/D converter 2 for reference level. Both the upper and lower limit reference voltages VRH and VRL set previously at prescribed levels are supplied to the converter 2 from a control part together with a sampling clock phiS of 3.12MHz, for example. Thus the converter 2 compares the VRH with VRL and decides a white level if the video signal is higher than the level VRH to deliver a white digital signal W. While a black level is decided when the video signal is lower than the level VRL. Then a black digital signal is delivered.

公开(公告)号：JPS61205024A

公开(公告)日：1986-09-11

申请号：JP4603385

申请日：1985-03-08

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI ,  YAMAGISHI KOJI

IPC: H03M1/12 ,  H03M1/18 ,  H04N9/30 ,  H04N9/64 ,  H04N19/00

Abstract: PURPOSE:To control the level of the reference voltage from outside by using the reference voltage set by an A/D converting circuit for setting the reference voltage to give the A/D conversion to the TV video signal and at the same time feeding back the set reference voltage t said A/D converting circuit. CONSTITUTION:The working voltages V1 and V2 are supplied to an integration circuit 4; while the working voltages V1' and V2' are supplied to an integration circuit 5. The circuit 4 integrates the V1 and V2 in response to the signal given from a pulse producing circuit 2 and then delivers the integration output to a luminance A/D converting circuit 1 in the form of the upper limit reference voltage VH. Then the circuit 5 integrates the V1' and V2' in response to the signal sent from a pulse producing circuit 3 and delivers the integration output to the circuit 1 in the form of the lower reference voltage VL. The output of both circuits 4 and 5 undergo the level shifts through level shifters 6a-6c and are applied to a red A/D converting circuit 7a, a green A/D converting circuit 7b and a blue A/D converting circuit 7c in the form of upper and lower reference voltages VH' and VL' respectively.

公开(公告)号：JP2010141911A

公开(公告)日：2010-06-24

申请号：JP2010017516

申请日：2010-01-29

Applicant: Casio Computer Co Ltd ,  カシオ計算機株式会社

Inventor： NAKAGOME KOICHI ,  ONODERA YUTAKA ,  MATSUI SHINICHI

IPC: H04N5/232 ,  H04N5/225 ,  H04N5/91 ,  H04N101/00

Abstract: PROBLEM TO BE SOLVED: To provide an image recording method capable of stably running an automatic recording process.
SOLUTION: An image recording method includes: an initial setting step of generating a predetermined number of retrieval points in a certain area of an image; a filtering step of updating the coordinates of a plurality of retrieval points using random numbers, comparing the feature quantity of the certain area with the feature quantity of the updated retrieval points in the image, giving weight in a way that it increases as similarity increases, filtering the retrieval points based on the weight, calculating distribution of the coordinates of the filtered retrieval points, and calculating a weighted average of the coordinates of the filtered retrieval points; and an image recording determining step of determining whether to record an image based on the distribution of the filtered retrieval points, the weighted average of the coordinates of the filtered retrieval points, and a tracking range, and recording the image when determination is made to record the image.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供能够稳定地进行自动记录处理的图像记录方法。 解决方案：一种图像记录方法包括：初始设置步骤，在图像的特定区域中产生预定数量的检索点; 使用随机数更新多个检索点的坐标的过滤步骤，将特定区域的特征量与图像中更新的检索点的特征量进行比较，以相似度增加的方式给出权重， 基于权重过滤检索点，计算经滤波的检索点的坐标分布，以及计算经滤波的检索点坐标的加权平均值; 以及图像记录确定步骤，用于基于滤波的检索点的分布，滤波的检索点的坐标的加权平均值和跟踪范围来确定是否记录图像，以及当确定进行记录时记录图像 图片。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2001356793A

公开(公告)日：2001-12-26

申请号：JP2000176895

申请日：2000-06-13

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI

IPC: G10L15/14

Abstract: PROBLEM TO BE SOLVED: To provide a voice recognition device and a voice recognizing method capable of performing voice recognition adapted to the speaking speed of a speaker even if the model adapted to the speaking speed is not spherically prepared. SOLUTION: A featured values adjusting part 4 adjusts differential featured values of respective frames obtained in a differential featured values detecting part 2 so as to be inversely proportional to a speaking speed as to an input voice which is obtained as an average differential amount in an average differential amount detecting part 3 and replaces the differential featured values being detected with these adjusted featured values and the input voice is recognized by probability computation based on hidden Markov models 151 to 15n in a comparator part 14.

公开(公告)号：JPH1051789A

公开(公告)日：1998-02-20

申请号：JP20740896

申请日：1996-08-06

Applicant: CASIO COMPUTER CO LTD

Inventor： MATSUI SHINICHI

IPC: H04N19/50 ,  H03M7/36 ,  H04N19/107 ,  H04N19/134 ,  H04N19/139 ,  H04N19/172 ,  H04N19/176 ,  H04N19/196 ,  H04N19/423 ,  H04N19/503 ,  H04N19/51 ,  H04N19/65 ,  H04N19/85 ,  H04N7/32

Abstract: PROBLEM TO BE SOLVED: To recover an error quickly with respect to a motion area and to suppress a data quantity. SOLUTION: A VRAM 1 stores dynamic data received sequentially in the unit of frames. An area discrimination section 3 divides an image stored in the VRAM 1 into a plurality of blocks and discriminates whether each block belongs to an moving region or a still region. A coding setting section 4 sets a block to apply inframe coding processing to the still and moving regions at a rate of 1:2. An inner processing section 5 applies in-frame coding to the block to which the in-frame coding processing is set. On the other hand, an intra processing section 6 applies in-frame motion compensation coding to blocks to which the in-frame coding processing is not set. Furthermore, the coding setting section 4 shifts a prescribed number of blocks each for each frame for the blocks to which the in-frame coding processing is set.