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11.发明申请公开(公告)号：US20180146155A1
公开(公告)日：2018-05-24
申请号：US15653358
申请日：2017-07-18
Inventor： Chun-Gi LYUH , Yi-Gyeong KIM , Jung Hee SUK , Young-Deuk JEON , Min-Hyung CHO
CPC classification number: H04N5/4448 , H04N5/05 , H04N5/23238 , H04N19/44
Abstract: The present disclosure relates to a frame grabber, an image processing system, and an image processing method. A frame grabber according to an embodiment of the inventive concept includes a plurality of decoders, a plurality of image controllers, a plurality of memories, a synchronization controller, and a synchronization memory. The plurality of decoders generate a plurality of image data by decoding a plurality of image signals. The plurality of image controllers generate a plurality of pixel data and a plurality of frame information data on the basis of the plurality of image data. The plurality of memories store the plurality of pixel data. The synchronization controller receives the plurality of frame information data, and generates synchronization data on the basis of the plurality of frame information data. The synchronization memory stores the frame information data and the synchronization data.
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12.发明申请公开(公告)号：US20250158604A1
公开(公告)日：2025-05-15
申请号：US18940129
申请日：2024-11-07
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO
Abstract: Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.
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公开(公告)号：US20210357753A1
公开(公告)日：2021-11-18
申请号：US17317607
申请日：2021-05-11
Inventor： Jin Kyu KIM , Byung Jo KIM , Seong Min KIM , Ju-Yeob KIM , Ki Hyuk PARK , Mi Young LEE , Joo Hyun LEE , Young-deuk JEON , Min-Hyung CHO
Abstract: A method and apparatus for multi-level stepwise quantization for neural network are provided. The apparatus sets a reference level by selecting a value from among values of parameters of the neural network in a direction from a high value equal to or greater than a predetermined value to a lower value, and performs learning based on the reference level. The setting of a reference level and the performing of learning are iteratively performed until the result of the reference level learning satisfies a predetermined value and there is no variable parameter that is updated during learning among the parameters.
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Patent Agency Ranking
公开(公告)号：US20250157499A1
公开(公告)日：2025-05-15
申请号：US18820449
申请日：2024-08-30
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO
Abstract: Disclosed herein is a reference voltage calibration apparatus in a memory interface. The reference voltage calibration apparatus includes a first low-pass filter configured to receive a clock signal, a second low-pass filter configured to receive an inverted clock signal that is an inverted signal of the clock signal, a first comparator configured to compare an output of the first low-pass filter with a reference voltage, a second comparator configured to compare an output of the second low-pass filter with the reference voltage, an up/down counter configured to count upward or downward from output values of the first comparator and the second comparator, respectively, and a digital-to-analog converter configured to convert an up/down counter value into an analog signal, and then output the reference voltage, wherein the digital-to-analog converter applies a calibration voltage based on the reference voltage to the first low-pass filter and to the second low-pass filter.
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15.发明公开公开(公告)号：US20230147293A1
公开(公告)日：2023-05-11
申请号：US17983016
申请日：2022-11-08
Inventor： Min-Hyung CHO , Young-Deuk JEON , Jin Ho HAN
IPC: G11C11/4099 , G11C5/06 , G11C5/04
CPC classification number: G11C11/4099 , G11C5/063 , G11C5/04
Abstract: A method for ZQ calibration for a data transmission driving circuit of each memory die in a memory chip package in which memory dies are stacked, includes generating a reference current through a reference resistor connected between a power terminal supplying a power voltage of the data transmission driving circuit and a ground terminal and a first transistor that is diode-connected; supplying first currents corresponding to the reference currents to a pull-up driver of each memory die; performing ZQ calibration of a pull-up driver of a corresponding memory die by comparing a first voltage formed by each first current with a reference voltage formed by the reference current in each of the plurality of memory dies; and performing ZQ calibration of a pull-down driver of the corresponding memory die based on an output impedance of the ZQ calibrated pull-up driver in each of the memory dies.
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公开(公告)号：US20210184677A1
公开(公告)日：2021-06-17
申请号：US16996389
申请日：2020-08-18
Inventor： Min-Hyung CHO , Young-deuk JEON , Seong Min KIM
IPC: H03K19/017 , H03K19/17784 , H03K19/096 , H03K19/08
Abstract: Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.
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公开(公告)号：US20190239771A1
公开(公告)日：2019-08-08
申请号：US16248582
申请日：2019-01-15
Inventor： Min-Hyung CHO , Young-deuk JEON , Bon Tae KOO , Mun Yang PARK , Youngseok BAEK
IPC: A61B5/053 , G01N27/02 , G01N33/483 , A61B5/00
CPC classification number: A61B5/0537 , A61B5/4869 , A61B5/7278 , G01N27/028 , G01N33/4833
Abstract: The inventive concept relates to a body composition analysis system. A body composition analysis system according to an embodiment of the inventive concept includes a sinusoidal signal generator, a synchronous detector, and a bioimpedance analyzer. The sinusoidal signal generator converts a digital sinusoidal signal having a target frequency into an analog sinusoidal signal. The synchronous detector extracts a target frequency component of a bioelectrical signal generated in response to an analog sinusoidal signal based on the digital sinusoidal signal. The bioimpedance analyzer calculates the bioimpedance based on the target frequency component of the bioelectrical signal. According to the inventive concept, it is possible to improve the selectivity for extracting the target frequency component of the bioelectrical signal and to reduce the area and variations of characteristics for the implementation of the integrated circuit.
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公开(公告)号：US20180143646A1
公开(公告)日：2018-05-24
申请号：US15804992
申请日：2017-11-06
Inventor： Jung Hee SUK , Yi-Gyeong KIM , Chun-Gi LYUH , Young-Deuk JEON , Min-Hyung CHO
Abstract: Provided are an object recognition device, an autonomous driving system including the same, and an object recognition method using the object recognition device. The object recognition device includes an object frame information generation unit, a frame analysis unit, an object priority calculator, a frame complexity calculator, and a mode control unit. The object frame information generation unit generates object frame information based on a mode control signal. The frame analysis unit generates object tracking information based on object frame information. The object priority calculator generates based on object tracking information. The frame complexity calculator generates a frame complexity based on object tracking information. The mode control unit generates a mode control signal for adjusting an object recognition range and a calculation amount of the object frame information generation unit based on the priority information, the frame complexity, and the resource occupation state.
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