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公开(公告)号：US20240195400A1
公开(公告)日：2024-06-13
申请号：US18454507
申请日：2023-08-23
Inventor： Min-Hyung CHO , Yi-Gyeong KIM , Su-Jin PARK , Young-Deuk JEON
CPC classification number: H03K7/08 , H03K5/05 , H03K5/131 , H03K5/15066
Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
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公开(公告)号：US20240163139A1
公开(公告)日：2024-05-16
申请号：US18506544
申请日：2023-11-10
Inventor： Young-deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H04L25/03057 , G06F13/16 , H04L25/0272 , G06F2213/16
Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
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公开(公告)号：US20190213471A1
公开(公告)日：2019-07-11
申请号：US16222867
申请日：2018-12-17
Inventor： Young-deuk JEON , Min-Hyung CHO
IPC: G06N3/063
Abstract: Provided is a neuromorphic computing device including a differential signal generator configured to generate a plurality of first differential signals and a plurality of second differential signals on a basis of bits generated according to computation of each of a plurality of pieces of input data and each of a plurality of pieces of weight data corresponding thereto, a first capacitor synapse array configured to sample the plurality of pieces of first differential signals and output a first output voltage, a second capacitor synapse array configured to sample the plurality of pieces of second differential signals and output a second output voltage, a comparator configured to compare the first output voltage with the second output voltage to output a comparison result, and a successive approximation register (SAR) logic configured to control the first capacitor synapse array and the second capacitor synapse array on a basis of the comparison result and generate intermediate data.
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公开(公告)号：US20240194241A1
公开(公告)日：2024-06-13
申请号：US18223097
申请日：2023-07-18
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
IPC: G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
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公开(公告)号：US20200174751A1
公开(公告)日：2020-06-04
申请号：US16695509
申请日：2019-11-26
Inventor： Min-Hyung CHO , Young-deuk JEON , Ki Hyuk PARK , Joo Hyun LEE
Abstract: The neuromorphic arithmetic device performs a multiply-accumulate (MAC) calculation using a multiplier and an accumulator. The neuromorphic arithmetic device includes an offset accumulator configured to receive a plurality of offset data measured a plurality of times and accumulate the plurality of offset data, a bit extractor configured to obtain average offset data by extracting at least one first bit from the plurality of accumulated offset data, and a cumulative synapse array configured to accumulate a plurality of multiplication values generated by the multiplier and output a cumulative result of the plurality of multiplication values corrected according to the average offset data.
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Patent Agency Ranking
公开(公告)号：US20180138882A1
公开(公告)日：2018-05-17
申请号：US15684625
申请日：2017-08-23
Inventor： Yi-Gyeong KIM , Woo Seok YANG , Min-Hyung CHO
IPC: H03G3/30
CPC classification number: H03G3/3089 , H03G3/3005 , H03G3/3026 , H04R1/08 , H04R3/00 , H04R2410/03
Abstract: The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise.
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公开(公告)号：US20240195399A1
公开(公告)日：2024-06-13
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H03K5/1565 , G06F1/12 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/0812 , H03K2005/00058
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US20220301603A1
公开(公告)日：2022-09-22
申请号：US17565937
申请日：2021-12-30
Inventor： Young-Deuk JEON , Min-Hyung CHO , Young-Su KWON , Jin Ho HAN
Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
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公开(公告)号：US20210151091A1
公开(公告)日：2021-05-20
申请号：US16997445
申请日：2020-08-19
Inventor： Young-deuk JEON , Seong Min KIM , Jin Kyu KIM , Joo Hyun LEE , Min-Hyung CHO , Jin Ho HAN
IPC: G11C11/4076 , G11C11/4099 , G11C11/4096
Abstract: Disclosed are a device and a method for calibrating a reference voltage. The reference voltage calibrating device includes a data signal communication unit that transmits/receives a data signal, a data strobe signal receiving unit that receives a first data strobe signal and a second data strobe signal, a voltage level of the second data strobe signal being opposite to a voltage level of the first data strobe signal, and a reference voltage generating unit that sets a reference voltage for determining a data value of the data signal, based on the first data strobe signal and the second data strobe signal, and the reference voltage generating unit adjusts the reference voltage based on the first data strobe signal and the second data strobe signal.
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公开(公告)号：US20200226456A1
公开(公告)日：2020-07-16
申请号：US16742808
申请日：2020-01-14
Inventor： Young-deuk JEON , Byung Jo KIM , Ju-Yeob KIM , Jin Kyu KIM , Ki Hyuk PARK , Mi Young LEE , Joo Hyun LEE , Min-Hyung CHO
Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.
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