公开(公告)号：JP2006338689A

公开(公告)日：2006-12-14

申请号：JP2006244432

申请日：2006-09-08

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G06F12/00 ,  G06F1/04 ,  G06F1/18 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To provide a memory system, which stably operates in a high frequency, has a topology not requiring consideration for an effect caused by a radiation noise, and has a varied wiring topology for data and command address signals. SOLUTION: In the memory system comprising a plurality modules, each of which is provided with a plurality of DRAMs, each of the DRAMs and a memory controller (MC) is connected with a data wiring and clock wiring. The clock wiring has a specific topology for each module in the manner similar to a command address wiring. The data wiring, also, has a topology for connecting a corresponding DRAM on each module. As a result, a clock and command address wiring has a topology, which is shorter than that of the clock wiring. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供稳定地高频操作的存储系统，具有不需要考虑由辐射噪声引起的影响的拓扑，并且具有用于数据和命令地址信号的变化的布线拓扑。 解决方案：在包括多个模块的存储器系统中，每个模块设置有多个DRAM，每个DRAM和存储器控制器（MC）都与数据线和时钟布线连接。 时钟接线以类似于命令地址布线的方式为每个模块提供特定拓扑。 数据线也具有用于连接每个模块上相应DRAM的拓扑结构。 因此，时钟和命令地址布线具有比时钟布线更短的拓扑结构。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004327474A

公开(公告)日：2004-11-18

申请号：JP2003115834

申请日：2003-04-21

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI ,  KANNO TOSHIO ,  IKEDA HIROAKI

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To solve the problem that a memory module having a plurality of DRAM chips which transmit and receive internal data signals having broader data widths and slower transfer rates than system data signals have, by transmitting and receiving the system data signals at a prescribed data width and transfer rate has a limit in the transfer rate of the system data signals and is not able to increase the transfer rate and, in addition, the DRAMs constituting the memory module consume large quantities of currents and also prevent the increase in the transfer rate. SOLUTION: The memory module is provided with a constitution which is formed by laminating a plurality of DRAM chips upon an IO chip and connecting the DRAM chips to the IO chip by means of through electrodes and converts the system data signals and internal data signals in the DRAM chips to each other in the IO chip. In this constitution, the wiring among the DRAM chips can be shortened and, at the same time, it is sufficient to install a DLL which consumes a large quantity of current to the IO chip only. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题为了解决具有发送和接收具有比系统数据信号更宽的数据宽度和较慢传输速率的内部数据信号的多个DRAM芯片的存储模块的存储模块，通过发送和接收系统数据 以规定的数据宽度和传送速率的信号对系统数据信号的传送速率具有限制，并且不能增加传送速率，另外，构成存储器模块的DRAM消耗大量电流，并且还防止 增加转移率。 解决方案：存储器模块具有通过在IO芯片上层叠多个DRAM芯片并且通过通过电极将DRAM芯片连接到IO芯片而形成的结构，并且将系统数据信号和内部数据 在DRAM芯片中的信号彼此在IO芯片中。 在这种结构中，可以缩短DRAM芯片之间的布线，并且同时，仅将IO消耗大量电流的DLL安装到IO芯片就足够了。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004021409A

公开(公告)日：2004-01-22

申请号：JP2002172939

申请日：2002-06-13

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406

CPC classification number: G11C7/109 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C2207/2254

Abstract: PROBLEM TO BE SOLVED: To provide a memory system having topology requiring no consideration of influences of radiation noises and stably operating even in a high frequency. SOLUTION: The memory system comprises a plurality of modules 51, 52 and a plurality of DRAMs 56 provided thereon, respectively, each of the DRAMs 56 being connected to a memory controller (MC) via data wiring and clock wiring. The clock wiring has topology dedicated to each of the modules 51, 52, while the data wiring has topology for connecting the corresponding DRAM 56 on each of the modules 51, 52. Command address wiring also has topology similar to that of the clock wiring. Herein, a data signal and a clock/command address signal to be given through the clock wiring/command address wiring are transmitted/received to/from the DRAM 56 and MC at different timings. A circuit is therefore provided in the DRAM 56 and the MC for matching the timings to each other. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2013137844A

公开(公告)日：2013-07-11

申请号：JP2011287492

申请日：2011-12-28

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： TANAKA YUKI ,  MORISHITA TETSUJI ,  MATSUI YOSHINORI

IPC: G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which allows a command address signal to be inputted to a semiconductor chip with an appropriate command by monitoring and adjusting timing difference between an external clock signal and a CA signal.SOLUTION: A semiconductor device includes: a first circuit 10 which activates a third control signal MDCACALC in response to a shift of a second control signal CKE from an activated state (High) to an inactivated state (Low), which allows an internal clock signal to be supplied when in the activated state, if a first control signal MDCACAL is indicating a calibration mode; a second circuit 30 which activates a fourth control signal LAT_TRIG in synchronization with an external clock signal CLK when the third control signal MDCACALC is in the activated state; and a third circuit 40 which latches an inputted command address signal CA in response to the activation of the fourth control signal LAT_TRIG.

Abstract translation: 要解决的问题：提供一种通过监视和调整外部时钟信号和CA信号之间的定时差，通过适当的命令将命令地址信号输入到半导体芯片的半导体器件。解决方案：一种半导体器件包括： 第一电路10，其响应于第二控制信号CKE从激活状态（高）移动到非激活状态（低）而激活第三控制信号MDCACALC，这允许在激活时提供内部时钟信号 状态，如果第一控制信号MDCACAL指示校准模式; 第二电路30，当第三控制信号MDCACALC处于激活状态时，其与外部时钟信号CLK同步地激活第四控制信号LAT_TRIG; 以及响应于第四控制信号LAT_TRIG的激活而锁存输入的命令地址信号CA的第三电路40。

公开(公告)号：JP2013009212A

公开(公告)日：2013-01-10

申请号：JP2011141374

申请日：2011-06-27

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: H03K19/0175 ,  G11C11/4096

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces power consumed by charging and discharging of a signal transfer line.SOLUTION: A semiconductor device includes: a receiver circuit R0k including an amplifier circuit AMP having a flip-flop configuration; and a transistor M7 disposed between a data bus DB and an input terminal T2 of the receiver circuit R0k, and turning off when a potential of the data bus DB reaches VPERI-NVth. Since an amplitude at the input terminal T2 is limited by the transistor M7, a transfer rate when changing the data bus DB from a low level to a high level is improved. Further, since the amplifier circuit AMP has the flip-flop configuration, no penetration current is generated after inversion of the flip-flop. Thereby, power consumption is further reduced.

Abstract translation: 要解决的问题：提供一种降低信号传输线的充电和放电消耗的功率的半导体器件。 解决方案：半导体器件包括：接收器电路R0k，其包括具有触发器配置的放大器电路AMP; 以及设置在数据总线DB和接收电路R0k的输入端子T2之间的晶体管M7，当数据总线DB的电位达到VPERI-NVth时，晶体管M7截止。 由于输入端子T2的幅度受到晶体管M7的限制，因此提高了将数据总线DB从低电平变为高电平时的传输速度。 此外，由于放大器电路AMP具有触发器配置，所以在触发器反相之后不产生穿透电流。 从而进一步降低功耗。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012044280A

公开(公告)日：2012-03-01

申请号：JP2010181329

申请日：2010-08-13

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: H03K5/14

CPC classification number: H03K5/04 ,  G11C7/04 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H03K5/133 ,  H03K5/153

Abstract: PROBLEM TO BE SOLVED: To cancel a delay time generated in a delay circuit, which is caused by fluctuation in a temperature or a voltage.SOLUTION: In a delay circuit, a plurality of inverters INVo and INVe, each of which consists of an N-channel type first transistor and a P-channel type second transistor connected in series, are connected alternately. The delay circuit has a P-channel type third transistor connected between a power supply wire VDD and an input node 'in' of the inverter INVe. Due to the existence of the third transistor, characteristic fluctuation of the second transistor included in each of the plurality of inverters is canceled even when a temperature or a voltage or the like fluctuates. Thereby, when a temperature or a voltage or the like fluctuates, delay amount fluctuation in the whole delay circuit can be considered as characteristic fluctuation of the first transistor.

Abstract translation: 要解决的问题：消除由温度或电压的波动引起的延迟电路中产生的延迟时间。 解决方案：在延迟电路中，交替地连接多个逆变器INVo和INVe，每个反相器INVo和INVe由N沟道型第一晶体管和串联连接的P沟道型第二晶体管组成。 延迟电路具有连接在电源线VDD和反相器INVe的输入节点“in”之间的P沟道型第三晶体管。 由于第三晶体管的存在，即使当温度或电压等波动时，包含在多个逆变器中的第二晶体管的特性波动也被消除。 因此，当温度或电压等波动时，整个延迟电路的延迟量波动可以被认为是第一晶体管的特性波动。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011091708A

公开(公告)日：2011-05-06

申请号：JP2009244935

申请日：2009-10-23

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: H03K19/0175 ,  G11C11/4096 ,  H03K19/0948 ,  H04L25/49

CPC classification number: H03K19/0013 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  H03K19/018571

Abstract: PROBLEM TO BE SOLVED: To reduce electric power consumed by charging and discharging of a signal transmission line. SOLUTION: A semiconductor device includes a switching transistor M0 which is inserted between a data bus DB and an input end (a) of a signal receiving circuit 110 and turns off when the data bus DB reaches VPERI-NVth, and an assist transistor M2 which drives the input end (a) of the signal receiving circuit 110 to VPERI. The switching transistor M0 and assist transistor M2 assist in receiving operation of the signal receiving circuit 110, so the amplitude of a transferred signal can be reduced without lowering the transfer speed. Consequently, the electric power consumed by the charging and discharging of the data bus DB is reducible. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：减少信号传输线的充电和放电所消耗的电力。 解决方案：半导体器件包括插入在数据总线DB和信号接收电路110的输入端（a）之间的开关晶体管M0，当数据总线DB达到VPERI-NVth时，该开关晶体管M0被截止，并且辅助 晶体管M2，其将信号接收电路110的输入端（a）驱动到VPERI。 开关晶体管M0和辅助晶体管M2有助于接收信号接收电路110的操作，因此可以降低传送信号的幅度而不降低传送速度。 因此，能够减少数据总线DB的充放电所消耗的电力。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010040082A

公开(公告)日：2010-02-18

申请号：JP2008199843

申请日：2008-08-01

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI ,  KANEKO SHOJI

IPC: G11C29/12 ,  G11C11/401 ,  G11C29/34

CPC classification number: G11C29/00 ,  G11C7/1078 ,  G11C7/1087 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/48

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be tested satisfactorily even when only some of a plurality of data input/output terminals are connected to a memory tester, and to provide a method for testing the semiconductor memory device. SOLUTION: The semiconductor memory device includes: data input/output terminals (DQ0 to DQ31); a memory cell array 122; and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals in a normal writing operation and writing the data in the memory cell array with a delay. The data latch circuit 111 includes a test mode in which the data latch circuit latches the data read to the data input/output terminals in a read operation and writes the previously latched data in the memory cell array without newly latching data of the data input/output terminals in a write operation. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种可以令人满意地测试的半导体存储器件，即使只有一些数据输入/输出端子连接到存储器测试器，并且提供一种用于测试半导体存储器件的方法 。 解决方案：半导体存储器件包括：数据输入/输出端子（DQ0至DQ31）; 存储单元阵列122; 以及用于在正常写入操作中临时锁存从数据输入/输出端子捕获的数据并将数据以延迟写入存储单元阵列的数据锁存电路111。 数据锁存电路111包括测试模式，其中数据锁存电路在读取操作中锁存读取到数据输入/输出端的数据，并且将先前锁存的数据写入存储单元阵列中，而不用新锁存数据输入/ 输出端子进行写操作。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2013131277A

公开(公告)日：2013-07-04

申请号：JP2011281802

申请日：2011-12-22

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： SAKASHITA MOTOMASA ,  MORISHITA TETSUJI ,  MATSUI YOSHINORI ,  MATSUBARA YASUSHI

IPC: G11C29/12 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC classification number: H03K5/159 ,  G06F1/10 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K21/00 ,  H03K21/406 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To reduce variations of a delay time tAC.SOLUTION: A semiconductor device includes: a measuring circuit 200 for measuring propagation time of an internal clock signal CLKDQa; a delay adjustment circuit 100 for adjusting propagation time of the internal clock signal CLKDQa on the basis of a measurement result S by the measuring circuit 200; and a data output circuit 81R for synchronizing with the internal clock signal CLKDQa to output a data signal DQ. In this invention, the propagation time of the internal clock signal CLKDQa can be accurately measured even when using a tester of a low speed. Accordingly, the delay time tAC can be adjusted in a state of a semiconductor wafer, for instance, and variations of the delay time tAC between a plurality of semiconductor devices can be reduced.

Abstract translation: 要解决的问题：减少延迟时间tAC的变化。解决方案：半导体器件包括：用于测量内部时钟信号CLKDQa的传播时间的测量电路200; 延迟调整电路100，用于根据测量电路200的测量结果S调整内部时钟信号CLKDQa的传播时间; 以及与内部时钟信号CLKDQa同步以输出数据信号DQ的数据输出电路81R。 在本发明中，即使使用低速的测试仪，也可以精确地测量内部时钟信号CLKDQa的传播时间。 因此，例如，可以在半导体晶片的状态下调整延迟时间tAC，并且可以减少多个半导体器件之间的延迟时间tAC的变化。

公开(公告)号：JP2013125561A

公开(公告)日：2013-06-24

申请号：JP2011273433

申请日：2011-12-14

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C11/4076 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: G11C11/4096 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/107

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption during write operation.SOLUTION: A semiconductor device comprises: a divider circuit 100 that generates a plurality of frequency-dividing clock signals CLK0 to CLKn each having a different phase by frequency-dividing an external clock signal CK; a multiplication circuit 200 that generates an internal clock signal CLKDQ by multiplying the frequency-dividing clock signals CLK0 to CLKn; and a data input/output circuit 300. In read operation, the data input/output circuit 300 serially outputs a plurality of read data items, which are supplied in parallel, in synchronization with the internal clock signal CLKDQ; and in write operation, it outputs in parallel a plurality of write data items, which are serially supplied, in synchronization with the frequency dividing clock signal CLK0. Thus, it is not necessary to transmit all of the plurality of frequency-dividing clock signals CLK0 to CLKn each having a different phase during write operation, and consequently, power consumption during write operation is reduced.

Abstract translation: 要解决的问题：为了减少写入操作期间的功耗。 解决方案：半导体器件包括：除法器电路100，其通过对外部时钟信号CK进行分频来产生各自具有不同相位的多个分频时钟信号CLK0至CLKn; 乘法电路200，通过将分频时钟信号CLK0与CLKn相乘来产生内部时钟信号CLKDQ; 数据输入/输出电路300.在读取操作中，数据输入/输出电路300与内部时钟信号CLKDQ同步地串行地输出并行提供的多个读取数据项; 并且在写入操作中，与分频时钟信号CLK0同步地并行地输出串行提供的多个写入数据项。 因此，在写入操作期间不需要传送分别具有不同相位的多个分频时钟信号CLK0至CLKn，因此，写入操作期间的功耗降低。 版权所有（C）2013，JPO＆INPIT