公开(公告)号：KR20120082464A

公开(公告)日：2012-07-23

申请号：KR20127014233

申请日：2009-02-18

Applicant: ELPIDA MEMORY INC ,  TOKYO ELECTRON LTD

Inventor： KAWANO YUMIKO ,  ARIMA SUSUMU ,  KAKIMOTO AKINOBU ,  HIROTA TOSHIYUKI ,  KIYOMURA TAKAKAZU

IPC: H01L21/316

CPC classification number: H01L21/31691 ,  C23C16/40 ,  C23C16/409 ,  C23C16/45527 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/1227 ,  H01G4/33 ,  H01L28/40

Abstract: Sr-Ti-O계 막의 성막 방법은 처리용기내에 Ru막이 형성된 기판을 배치하고, 기체상의 Ti 원료와, 기체상의 Sr 원료와, 기체상의 산화제를 상기 처리용기내에 도입해서 Ru막 상에 두께 10㎚ 이하의 제 1 Sr-Ti-O계 막을 성막하는 것과, 제 1 Sr-Ti-O계 막을 어닐해서 결정화시키는 것과, 제 1 Sr-Ti-O계 막의 위에, 기체상의 Ti 원료와, 기체상의 Sr 원료와, 기체상의 산화제를 처리용기내에 도입하고 그 위에 제 2 Sr-Ti-O계 막을 성막하는 것과, 제 2 Sr-Ti-O계 막을 어닐해서 결정화시키는 것을 포함한다.

Abstract translation: 通过在Ru膜厚度在处理容器引入锶原料，并在Ti原料基座上的氧化剂，并且形成Ru膜设置在基板上的气体和气体中处理容器锶钛-O系膜沉积方法10㎚ 作为成膜的基于胶片的根据权利要求1通过退火结晶作为膜锶钛-O或以下，则1锶钛-O系统中，权利要求1的锶钛-O系过膜，钛材料和，SR气相的气相的 它包括凝固的原料和引入气态氧化剂到处理容器中，并如权利要求2锶钛-O在其上的薄膜淀积系统中，薄膜是在退火的2型锶钛-O确定。

公开(公告)号：KR20100133312A

公开(公告)日：2010-12-21

申请号：KR20100055052

申请日：2010-06-10

Applicant: ELPIDA MEMORY INC

Inventor： AIZAWA KAZUO ,  ASANO ISAMU ,  TOMINAGA JYUNJI ,  KOLOBOV ALEXANDER ,  FONS PAUL ,  SIMPSON ROBERT

IPC: H01L27/115 ,  G11C13/02

CPC classification number: H01L27/2409 ,  H01L27/2454 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/143

Abstract: PURPOSE: A solid-state memory device, a data processing system, and a data processing device thereof are provided to store information by reversibly diversifying a crystalline state. CONSTITUTION: A semiconductor memory device(10) includes an address latch circuit(21) including an address signal(ADD) and a command decoder(22) generating an internal command(ICMD) after decoding a command(CMD). A second interlayer insulating layer has a second through-hole. A recording circuit(26) comprises a reset circuit and a set circuit. A first interlayer insulating layer has a first through-hole.

Abstract translation: 目的：提供固态存储装置，数据处理系统及其数据处理装置，以通过可逆地多样化结晶状态来存储信息。 构成：在解码命令（CMD）之后，半导体存储器件（10）包括地址锁存电路（21），其包括地址信号（ADD）和产生内部命令（ICMD）的命令解码器（22）。 第二层间绝缘层具有第二通孔。 记录电路（26）包括复位电路和设定电路。 第一层间绝缘层具有第一通孔。

公开(公告)号：WO2009131902A2

公开(公告)日：2009-10-29

申请号：PCT/US2009/040902

申请日：2009-04-17

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC. ,  HASHIM, Imran ,  DE, Indranil ,  CHIANG, Tony ,  HAYWOOD, Edward ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  KUMAR, Pragati ,  MALHOTRA, Sandra ,  SHANKER, Sunil

Inventor： HASHIM, Imran ,  DE, Indranil ,  CHIANG, Tony ,  HAYWOOD, Edward ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  KUMAR, Pragati ,  MALHOTRA, Sandra ,  SHANKER, Sunil

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/31 ,  H01L21/205

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产 反应。

公开(公告)号：WO2011034536A1

公开(公告)日：2011-03-24

申请号：PCT/US2009/057371

申请日：2009-09-18

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC. ,  KUMAR, Pragati ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  SHANKER, Sunil ,  MALHOTRA, Sandra ,  HASHIM, Imran

Inventor： KUMAR, Pragati ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  SHANKER, Sunil ,  MALHOTRA, Sandra ,  HASHIM, Imran

IPC: H01L27/04 ,  H01L27/108

CPC classification number: C23C16/45531 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02304 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/65 ,  H01L28/75

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness ("EOT").

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，要生长电介质层的底部电极可以具有钌基表面。 钌表面与电介质层的晶格匹配（例如氧化钛，钛酸锶钛酸钡或钛酸钡锶）​​有助于促进金红石相氧化钛的生长，从而导致较高的介电常数和较低的有效氧化物厚度。 钌基材料还提供高功函数材料，导致较低的泄漏。 为了减轻与使用钌有关的成核延迟，可以采用基于钛的粘附层或胶层。 可以进一步采用预处理工艺，以增加有效的电容器板面积，从而进一步提高介电常数和有效的氧化物厚度（“EOT”）。

公开(公告)号：WO2009131902A3

公开(公告)日：2010-03-11

申请号：PCT/US2009040902

申请日：2009-04-17

Applicant: INTERMOLECULAR INC ,  ELPIDA MEMORY INC ,  HASHIM IMRAN ,  DE INDRANIL ,  CHIANG TONY ,  HAYWOOD EDWARD ,  CHEN HANHONG ,  FUCHIGAMI NOBI ,  KUMAR PRAGATI ,  MALHOTRA SANDRA ,  SHANKER SUNIL

Inventor： HASHIM IMRAN ,  DE INDRANIL ,  CHIANG TONY ,  HAYWOOD EDWARD ,  CHEN HANHONG ,  FUCHIGAMI NOBI ,  KUMAR PRAGATI ,  MALHOTRA SANDRA ,  SHANKER SUNIL

IPC: H01L21/8242 ,  H01L21/205 ,  H01L21/31 ,  H01L27/108

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产 反应。

公开(公告)号：DE102006031862B4

公开(公告)日：2011-07-07

申请号：DE102006031862

申请日：2006-07-10

Applicant: ELPIDA MEMORY INC

Inventor： TSUKADA SHUICHI

IPC: G11C7/02 ,  G05F1/10 ,  G11C11/407 ,  G11C29/24

Abstract: Strombegrenzungsschaltung mit: einem Strombegrenzungselement zur Begrenzung eines Ausgangsstrompegels innerhalb eines vorbestimmten Bereichs eines Begrenzungsstroms und mit einem ersten PMOS-Transistor, an dessen Source eine vorbestimmte Spannung angelegt ist, und mit einem Drain, durch den der Ausgangsstrom gespeist wird; und einer Gate-Spannungserzeugungsschaltung zum Erzeugen einer Gate-Spannung durch eine Rückkopplungssteuerung, so dass die Der Gate-Spannung des ersten PMOS-Transistors mit einer Schwellwertspannung eines zweiten PMOS-Transistors übereinstimmt, der annähernd die gleiche Charakteristik wie der erste PMOS-Transistor hat, in einem Zustand, bei dem durch den zweiten PMOS-Transistor ein vorbestimmter Strom fließt.

公开(公告)号：DE102004036455B4

公开(公告)日：2010-01-21

申请号：DE102004036455

申请日：2004-07-28

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO ,  KOBAYASHI SHOTARO

IPC: G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/04 ,  H03K5/13 ,  H03L7/081 ,  H03L7/087

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

公开(公告)号：DE10130752B4

公开(公告)日：2009-12-31

申请号：DE10130752

申请日：2001-06-26

Applicant: ELPIDA MEMORY INC

Inventor： YANAGISAWA TAKESHI

IPC: G11C8/08 ,  G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/408 ,  H03K3/03 ,  H03K3/70

Abstract: A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.

公开(公告)号：DE10334531B4

公开(公告)日：2009-07-09

申请号：DE10334531

申请日：2003-07-29

Applicant: ELPIDA MEMORY INC

Inventor： SHIBATA KAYOKO ,  NISHIO YOJI ,  FUNABA SEIJI

IPC: G06F13/00 ,  G06F13/16 ,  G06F12/00 ,  G11C5/06 ,  G11C11/4063 ,  H05K1/02

Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N-1)xZeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N-1)xZeffdimm/N 2 .

公开(公告)号：DE69936277D1

公开(公告)日：2007-07-26

申请号：DE69936277

申请日：1999-04-26

Applicant: ELPIDA MEMORY INC

Inventor： TANIGUCHI JUNYA ,  KOSHIKAWA YASUJI ,  MINE KOUJI

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/317 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/14 ,  G11C29/56

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).