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公开(公告)号：US12206420B2
公开(公告)日：2025-01-21
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong Kim , Young-Su Kwon , Su-Jin Park , Young-Deuk Jeon , Min-Hyung Cho , Jae-Woong Choi
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US12087392B2
公开(公告)日：2024-09-10
申请号：US17565937
申请日：2021-12-30
Inventor： Young-Deuk Jeon , Min-Hyung Cho , Young-Su Kwon , Jin Ho Han
CPC classification number: G11C7/1084 , G11C7/1057 , G11C7/225 , G11C8/18
Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
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公开(公告)号：US11507811B2
公开(公告)日：2022-11-22
申请号：US16813901
申请日：2020-03-10
Inventor： Hyun Kyu Yu , Young-Su Kwon , Joo Hyun Lee
Abstract: An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.
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公开(公告)号：US11341066B2
公开(公告)日：2022-05-24
申请号：US17119387
申请日：2020-12-11
Inventor： Jin Ho Han , Min-Seok Choi , Young-Su Kwon
IPC: G06F13/16 , G06F12/02 , G06F12/1081 , G06F13/28
Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
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公开(公告)号：US10983878B2
公开(公告)日：2021-04-20
申请号：US16694913
申请日：2019-11-25
Inventor： Jin Ho Han , Young-Su Kwon , Min-Seok Choi
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.
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Patent Agency Ranking
公开(公告)号：US10430301B2
公开(公告)日：2019-10-01
申请号：US15432588
申请日：2017-02-14
Inventor： Young-Su Kwon , Kyung Jin Byun , Nak Woong Eum
Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
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17.发明授权Method and apparatus for controlling operation voltage of processor core, and processor system including the same 有权用于控制处理器核心的操作电压的方法和装置，以及包括其的处理器系统公开(公告)号：US09489034B2
公开(公告)日：2016-11-08
申请号：US14256402
申请日：2014-04-18
Inventor： Young-Su Kwon
CPC classification number: G06F1/3243 , G06F1/30 , Y02D10/152
Abstract: A method and an apparatus for controlling an operation voltage of a processor core and a processor system including the same are provided. The apparatus for controlling an operation voltage of a processor core includes a voltage supplier and an operation voltage searching core. The voltage supplier supplies the operation voltage to the processor core. The operation voltage searching core requests the processor core to execute a program, and controls the operation voltage based on whether the program has been normally operated.
Abstract translation: 提供了一种用于控制处理器核心和包括该处理器核心的处理器系统的操作电压的方法和装置。 用于控制处理器核心的操作电压的装置包括电压供应器和操作电压搜索核心。 电压供应器将操作电压提供给处理器内核。 操作电压搜索核心请求处理器核心执行程序，并且基于程序是否正常工作来控制操作电压。
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公开(公告)号：US12210952B2
公开(公告)日：2025-01-28
申请号：US16201871
申请日：2018-11-27
Inventor： Young-Su Kwon , Chan Kim , Hyun Mi Kim , Jeongmin Yang , Chun-Gi Lyuh , Jaehoon Chung , Yong Cheol Peter Cho
IPC: G06N3/04
Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.
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公开(公告)号：US11847465B2
公开(公告)日：2023-12-19
申请号：US17533788
申请日：2021-11-23
Inventor： Chun-Gi Lyuh , Hyun Mi Kim , Young-Su Kwon , Jin Ho Han
CPC classification number: G06F9/3895 , G06F9/355 , G06F12/0207
Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.
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20.发明授权公开(公告)号：US11176395B2
公开(公告)日：2021-11-16
申请号：US16694899
申请日：2019-11-25
Inventor： Jin Ho Han , Young-Su Kwon , Yong Cheol Peter Cho , Min-Seok Choi
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores arranged in rows and columns and configured to perform a pattern recognition operation on an input feature using a kernel coefficient in response to each instruction, an instruction memory configured to provide the instruction to each of the plurality of nano cores, a feature memory configured to provide the input feature to each of the plurality of nano cores, a kernel memory configured to provide the kernel coefficients to the plurality of nano cores, and a functional safety processor core configured to receive a result of a pattern recognition operation outputted from the plurality of nano cores to detect the presence of a recognition error, and perform a fault tolerance function on the detected recognition error.
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