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公开(公告)号：US12231100B2
公开(公告)日：2025-02-18
申请号：US17903112
申请日：2022-09-06
Inventor： Yi-Gyeong Kim , Young-Deuk Jeon , Young-Su Kwon , Jin-Ho Han
Abstract: An apparatus for receiving a strobe signal may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.
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公开(公告)号：US11782835B2
公开(公告)日：2023-10-10
申请号：US17536573
申请日：2021-11-29
Inventor： Joo-Hyun Lee , Young-Su Kwon , Jin-Ho Han
IPC: G06F12/08 , G06F8/60 , G06F8/41 , G06F12/084
CPC classification number: G06F12/084 , G06F8/44 , G06F8/60 , G06F2212/657
Abstract: Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.
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公开(公告)号：US11036595B2
公开(公告)日：2021-06-15
申请号：US16117403
申请日：2018-08-30
Inventor： Jin Ho Han , Min-Seok Choi , Young-Su Kwon
Abstract: Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.
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公开(公告)号：US10740167B2
公开(公告)日：2020-08-11
申请号：US15832862
申请日：2017-12-06
Inventor： Jin Ho Han , Young-Su Kwon
IPC: G06F11/00 , G06F11/07 , G06F12/0815 , G06F12/0804 , G06F12/0868 , G06F11/16
Abstract: A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.
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公开(公告)号：US10127098B2
公开(公告)日：2018-11-13
申请号：US15008188
申请日：2016-01-27
Inventor： Young-Su Kwon
Abstract: An apparatus and method for recovering the functionality of central processing unit core are disclosed herein. The apparatus for recovering the functionality of a central processing unit (CPU) core includes a functionality recovery buffer and a functionality recovery module unit. The functionality recovery buffer temporarily stores a value, to be stored in a register storage unit, in response to a write operation. The functionality recovery module unit performs the recovery of functionality by controlling the functionality recovery buffer when receiving a signal, indicating that a failure has been detected, from the outside.
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Patent Agency Ranking
公开(公告)号：US09632894B2
公开(公告)日：2017-04-25
申请号：US14677297
申请日：2015-04-02
Inventor： Jin-Ho Han , Young-Su Kwon , Kyung-Jin Byun
CPC classification number: G06F11/2215
Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
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公开(公告)号：US11507429B2
公开(公告)日：2022-11-22
申请号：US16038243
申请日：2018-07-18
Inventor： Chun-Gi Lyuh , Young-Su Kwon , Chan Kim , Hyun Mi Kim , Jeongmin Yang , Jaehoon Chung , Yong Cheol Peter Cho
Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.
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公开(公告)号：US11494623B2
公开(公告)日：2022-11-08
申请号：US16206687
申请日：2018-11-30
Inventor： Yong Cheol Peter Cho , Young-Su Kwon
Abstract: A processing element and an operating method thereof in a neural network are disclosed. The processing element may include a first multiplexer selecting one of a first value stored in a first memory and a second value stored in a second memory, a second multiplexer selecting one of a first data input signal and an output value of the first multiplexer, a third multiplexer selecting one of the output value of the first multiplexer and a second data input signal, a multiplier multiplying an output value of the second multiplexer by an output value of the third multiplexer, a fourth multiplexer for selecting one of the output value of the second multiplexer and an output value of the multiplier, and a third memory storing an output value of the fourth multiplexer.
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公开(公告)号：US20180165246A1
公开(公告)日：2018-06-14
申请号：US15832824
申请日：2017-12-06
Inventor： Jin Ho Han , Kyoung Seon Shin , Young-Su Kwon
IPC: G06F15/80 , G06F9/30 , G06F12/0842 , G06F11/07
Abstract: A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.
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公开(公告)号：US09823963B2
公开(公告)日：2017-11-21
申请号：US15006921
申请日：2016-01-26
Inventor： Jin-Ho Han , Young-Su Kwon
IPC: G06F12/00 , G06F11/10 , G06F12/0855 , G06F12/0831 , G06F12/128 , G06F12/0811 , G06F11/14
CPC classification number: G06F11/1064 , G06F11/141 , G06F12/0804 , G06F12/0811 , G06F12/0833 , G06F12/0855 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/621
Abstract: Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/store unit of a first processor; a level 0 cache #1 connected to the load/store unit of a second processor; and a fault detection and recovery unit for reading from and writing to tag memory, data memory, and valid bit memory of the level 0 cache #0 and the level 0 cache #1, performing the write-back and flush of the level 0 cache #0 and the level 0 cache #1 based on information stored therein, and instructing the load/store units of the first and second processors to stall a pipeline and to restart an instruction #n.
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