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公开(公告)号：CA2502841A1
公开(公告)日：2004-05-13
申请号：CA2502841
申请日：2003-10-23
Applicant: GCT SEMICONDUCTOR INC
Inventor： PARK JOONBAE , LEE JEONG-WOO , KOO YIDO , LEE KYEONGHO , AHN YOUNGHO , SONG EUNSEOK
Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase- locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.
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公开(公告)号：AU2003254188A1
公开(公告)日：2004-02-16
申请号：AU2003254188
申请日：2003-07-28
Applicant: GCT SEMICONDUCTOR INC
Inventor： LEE KYEONGHO , SONG EUNSEOK , LEE SEUNG-WOOK , LEE JEONG-WOO , PARK JOONBAE
Abstract: A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider that divides an input signal frequency by a predetermined value to produce an output signal frequency; and a frequency mixer that mixes the output signal frequency with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency. The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.
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公开(公告)号：AU767508B2
公开(公告)日：2003-11-13
申请号：AU1600501
申请日：2000-11-13
Applicant: GCT SEMICONDUCTOR INC
Inventor： LEE KYEONGHO , JEONG DEOG-KYOON , PARK JOONBAE , KIM WONCHAN
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公开(公告)号：CA2442721A1
公开(公告)日：2002-09-26
申请号：CA2442721
申请日：2002-03-20
Applicant: GCT SEMICONDUCTOR INC
Inventor： SONG EUNSEOK , HUH HYUNGKI , LEE KANG YOON , KOO YIDO , PARK JOONBAE , LEE JEONGWOO , LEE KYEONGHO
Abstract: A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phas e comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and- hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample - and-hold circuit.
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公开(公告)号：AU1600501A
公开(公告)日：2001-06-06
申请号：AU1600501
申请日：2000-11-13
Applicant: GCT SEMICONDUCTOR INC
Inventor： LEE KYEONGHO , JEONG DEOG-KYOON , PARK JOONBAE , KIM WONCHAN
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Patent Agency Ranking
公开(公告)号：AT450925T
公开(公告)日：2009-12-15
申请号：AT02757777
申请日：2002-03-27
Applicant: GCT SEMICONDUCTOR INC
Inventor： KANG SUWON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
Abstract: A wireless or wired communication system and method is provided including a transmitter and a receiver. A RF communication system in accordance with the present invention includes an apparatus and gain control method between RF receiver and baseband modem in case of a plurality of gain stages inside a receiver. The gain of each stage can be controlled by an integrated gain controller. The gain controller monitors the signal level of each gain stage to place its gain to optimal value. The gain control apparatus and method can be implemented in a digital AGC system. The gain controller accepts a signal implementing gain control and thus there is no stability issue. When distributed gain stages are present inside a related art receiver and separate gain control loops are used, stability issues can arise. In a preferred embodiment of an apparatus and method, the baseband modem decides the amount of gain control and adjusts the gain of certain gain stages by the proper amount.
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公开(公告)号：AT431009T
公开(公告)日：2009-05-15
申请号：AT02757825
申请日：2002-03-28
Applicant: GCT SEMICONDUCTOR INC
Inventor： JEONG HOE-SAM , LEE SEUNG-WOOK , LEE WON-SEOK , PARK JOONBAE , LEE KYEONGHO
Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.
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公开(公告)号：DE60225426T2
公开(公告)日：2009-03-12
申请号：DE60225426
申请日：2002-03-20
Applicant: GCT SEMICONDUCTOR INC
Inventor： HUH HYUNGKI , SONG EUNSEOK , LEE KANG YOON , KOO YIDO , LEE JEONGWOO , PARK JOONBAE , LEE KYEONGHO
Abstract: A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.
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公开(公告)号：DE60225426D1
公开(公告)日：2008-04-17
申请号：DE60225426
申请日：2002-03-20
Applicant: GCT SEMICONDUCTOR INC
Inventor： HUH HYUNGKI , SONG EUNSEOK , LEE KANG YOON , KOO YIDO , LEE JEONGWOO , PARK JOONBAE , LEE KYEONGHO
Abstract: A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.
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公开(公告)号：AT388541T
公开(公告)日：2008-03-15
申请号：AT02723501
申请日：2002-03-20
Applicant: GCT SEMICONDUCTOR INC
Inventor： HUH HYUNGKI , SONG EUNSEOK , LEE KANG YOON , KOO YIDO , LEE JEONGWOO , PARK JOONBAE , LEE KYEONGHO
Abstract: A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.
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