公开(公告)号：US11145725B2

公开(公告)日：2021-10-12

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Qizhi Liu ,  Vibhor Jain ,  Judson R. Holt ,  Herbert Ho ,  Claude Ortolland ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US11719895B1

公开(公告)日：2023-08-08

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251 ,  G02B1/00

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US11567266B1

公开(公告)日：2023-01-31

申请号：US17551377

申请日：2021-12-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson Holt ,  Yusheng Bian ,  Qizhi Liu ,  Elizabeth Strehlow

IPC: G02B6/34 ,  G02B6/124 ,  G02B6/12 ,  G02B6/293 ,  G02B6/42

Abstract: Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The structure includes a grating coupler having a central portion and edge portions. The central portion and the edge portions define a sidewall, and the central portion and the edge portions have a first longitudinal axis along which the edge portions are arranged in a spaced relationship. Each edge portion projects from the sidewall at an angle relative to the first longitudinal axis. A waveguide core is optically coupled to the grating coupler. The first longitudinal axis is aligned in a first direction, and the waveguide core has a second longitudinal axis that is aligned in a second direction different from the first direction.

公开(公告)号：US20220291446A1

公开(公告)日：2022-09-15

申请号：US17197133

申请日：2021-03-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Qizhi Liu

IPC: G02B6/124 ,  G02B6/13

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a semiconductor waveguide on a semiconductor layer. The semiconductor waveguide includes a first vertical sidewall over the semiconductor layer over the semiconductor layer. A plurality of grating protrusions extends horizontally from the first vertical sidewall of the semiconductor waveguide.

公开(公告)号：US20220254774A1

公开(公告)日：2022-08-11

申请号：US17173611

申请日：2021-02-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Vibhor Jain ,  Anthony K. Stamper ,  Qizhi Liu ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/732

Abstract: Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

公开(公告)号：US11374092B2

公开(公告)日：2022-06-28

申请号：US16784813

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Pekarik ,  Vibhor Jain ,  Herbert Ho ,  Claude Ortolland ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

公开(公告)号：US11195925B2

公开(公告)日：2021-12-07

申请号：US16732755

申请日：2020-01-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Qizhi Liu ,  Ramsey Hazbun ,  Pernell Dongmo ,  John J. Pekarik ,  Cameron E. Luce

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210098612A1

公开(公告)日：2021-04-01

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210091200A1

公开(公告)日：2021-03-25

申请号：US16788914

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.