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公开(公告)号：EP4550422A1
公开(公告)日：2025-05-07
申请号：EP24168351.5
申请日：2024-04-04
Applicant: GlobalFoundries U.S. Inc.
Inventor： BENTLEY, Steven J. , SHARMA, Santosh , KANTAROVSKY, Johnatan A. , LEVY, Mark D. , ZIERAK, Michael J.
IPC: H01L29/778 , H01L29/40 , H01L29/10 , H01L29/423
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.
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公开(公告)号：EP4535425A1
公开(公告)日：2025-04-09
申请号：EP24168621.1
申请日：2024-04-05
Applicant: GlobalFoundries U.S. Inc.
Inventor： Kim, Juhan , Parihar, Sanjay Rai , Rashed, Mahbub , Alpaslan, Zahir Yilmaz
Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.
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3.发明公开
公开(公告)号：EP4535414A1
公开(公告)日：2025-04-09
申请号：EP24168619.5
申请日：2024-04-05
Applicant: GlobalFoundries U.S. Inc.
Inventor： Jain, Navneet K. , Kim, Juhan , Rashed, Mahbub
IPC: H01L21/84 , H01L27/12 , H01L27/092
Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.
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公开(公告)号：EP4531112A1
公开(公告)日：2025-04-02
申请号：EP24163163.9
申请日：2024-03-13
Applicant: GlobalFoundries U.S. Inc.
Inventor： KAMMLER, Thorsten E. , BAARS, Peter , ZIER, Manfred Michael
IPC: H01L29/40 , H01L29/423 , H01L29/66 , B82Y10/00
Abstract: The present disclosure relates to a spin-qubit semiconductor devices and methods of manufacturing. The spin-qubit devices include on an SOI substrate: a plurality of barrier gates (12); a plurality of spin qubit gates (14), under which quantum dots are induced, and which are interdigitated with the plurality of barrier gates; two access gates (16) on opposing sides of the plurality of barrier gates, under which reservoirs are induced, a source region (22) and a drain region (22).
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公开(公告)号：EP4492667A1
公开(公告)日：2025-01-15
申请号：EP24151503.0
申请日：2024-01-12
Applicant: GlobalFoundries U.S. Inc.
Inventor： Hoffmann, Matthias
Abstract: To reduce sub-harmonic oscillations in a Switched-Mode Power Supply (SMPS). a ramp generator circuit of the SMPS produces a ramp signal having an amplitude corresponding to a sensed current through an energy storage device, such as an inductor, of the SMPS. The ramp signal is used to control a duty cycle of the SMPS. The ramp generator circuit may include a reference current circuit, a ramp capacitor, and a discharge circuit to periodically discharge the ramp capacitor. The ramp capacitor may be charged using a charging current produced by combining a feedback current corresponding to the sensed current with a reference current produced by the reference current circuit and may be periodically discharged at a fixed frequency, or may be charged using the reference current and discharged at a time determined according to the feedback current.
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Patent Agency Ranking
公开(公告)号：EP4468297A1
公开(公告)日：2024-11-27
申请号：EP23198971.6
申请日：2023-09-22
Applicant: GlobalFoundries U.S. Inc.
Inventor： Mueller, Johannes
Abstract: A magnetic memory device is provided. The magnetic memory device includes a first magnetic tunnel junction (MTJ) stack, a second MTJ stack, and a spin-orbit torque (SOT) electrode. The second MTJ stack is adjacent to the first MTJ stack. The SOT electrode is connected to the first MTJ stack and the second MTJ stack, wherein the SOT electrode has a first electrode section along a first axis and a second electrode section along a second axis, and the second axis is spaced apart from and parallel to the first axis.
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公开(公告)号：EP4462165A2
公开(公告)日：2024-11-13
申请号：EP23207846.9
申请日：2023-11-06
Applicant: GlobalFoundries U.S. Inc.
Inventor： BIAN, Yusheng
IPC: G02B6/12
Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.
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公开(公告)号：EP4455746A1
公开(公告)日：2024-10-30
申请号：EP23199991.3
申请日：2023-09-27
Applicant: GlobalFoundries U.S. Inc.
Inventor： DONEGAN, Keith , HOUGHTON, Thomas , BIAN, Yusheng , NUMMY, Karen , DEZFULIAN, Kevin , HIROKAWA, Takako
Abstract: Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.
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公开(公告)号：EP4447124A2
公开(公告)日：2024-10-16
申请号：EP24197793.3
申请日：2023-09-18
Applicant: GlobalFoundries U.S. Inc.
Inventor： JAIN, Vibhor , KENNEY, Crystal R. , PEKARIK, John J.
IPC: H01L29/786
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.
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公开(公告)号：EP4439140A1
公开(公告)日：2024-10-02
申请号：EP23196123.6
申请日：2023-09-08
Applicant: GlobalFoundries U.S. Inc.
Inventor： BIAN, Yusheng
CPC classification number: G02B6/305 , G02B6/4214 , G02B6/12002 , G02B6/125 , G02B6/1228
Abstract: Structures for an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate, a first waveguide core including a curved section and an end that terminates the curved section, and a second waveguide core including a section disposed adjacent to the curved section of the first waveguide core. The first waveguide core is positioned between the second waveguide core and the semiconductor substrate.
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