公开(公告)号：US20220037309A1

公开(公告)日：2022-02-03

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

公开(公告)号：US20240072038A1

公开(公告)日：2024-02-29

申请号：US17895153

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02 ,  H01L21/763

CPC classification number: H01L27/0262 ,  H01L21/763

Abstract: Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.

公开(公告)号：US20230420448A1

公开(公告)日：2023-12-28

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20230088425A1

公开(公告)日：2023-03-23

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/525

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US20220320073A1

公开(公告)日：2022-10-06

申请号：US17808647

申请日：2022-06-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.