公开(公告)号：US12107083B2

公开(公告)日：2024-10-01

申请号：US18462779

申请日：2023-09-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Meng Miao ,  Alain F. Loiseau ,  Souvick Mitra ,  You Li ,  Wei Liang

IPC: H01L27/02 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0259 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/0288 ,  H01L27/1207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

公开(公告)号：US11791626B2

公开(公告)日：2023-10-17

申请号：US17490371

申请日：2021-09-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/60

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0007

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US11430881B2

公开(公告)日：2022-08-30

申请号：US16810076

申请日：2020-03-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anindya Nath ,  Alain F. Loiseau

IPC: H01L29/04 ,  H01L29/74 ,  H01L29/73

Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.

公开(公告)号：US20220131369A1

公开(公告)日：2022-04-28

申请号：US17082182

申请日：2020-10-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Meng Miao ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

公开(公告)号：US20220037309A1

公开(公告)日：2022-02-03

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

公开(公告)号：US12205943B2

公开(公告)日：2025-01-21

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US20240028811A1

公开(公告)日：2024-01-25

申请号：US17813344

申请日：2022-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A process design kit (PDK) is supplied to a layout design tool. The PDK includes parameterized cells (Pcells) adapted to cause the layout design tool to automatically add labels to device layouts in the graphic design system (GDS) file that is being created by the layout design tool. Each corresponding label lists parameters used when creating the corresponding device layout. The GDS file is receive back from the layout design tool. The parameters from the labels is applied to corresponding ones of the Pcells within the PDK to create a device verification layout for each of the device layouts in the GDS file. Each of the device layouts in the GDS file is compared to a corresponding device verification layout. The device layouts within the GDS file that fail to match the corresponding device verification layout are thereby identified.

公开(公告)号：US11574867B2

公开(公告)日：2023-02-07

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/8249 ,  H01L21/02 ,  H01L27/07 ,  H01L23/62 ,  H01L27/115 ,  H01L27/112 ,  H01L27/02

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20220165663A1

公开(公告)日：2022-05-26

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/525 ,  H01L27/07 ,  H01L21/02 ,  H01L21/8249

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20240072038A1

公开(公告)日：2024-02-29

申请号：US17895153

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02 ,  H01L21/763

CPC classification number: H01L27/0262 ,  H01L21/763

Abstract: Embodiments of the disclosure provide a semiconductor controlled rectifier (SCR) structure and methods to form the same. The SCR structure may include a first polycrystalline semiconductor material on a first insulator and includes a first well therein. A monocrystalline semiconductor material is adjacent the first polycrystalline semiconductor material and includes an anode region and a cathode region therein. A second polycrystalline semiconductor material is on a second insulator and includes a second well therein.