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    ITERATIVE WRITE SEQUENCE INTERRUPT
    11.
    发明申请
    ITERATIVE WRITE SEQUENCE INTERRUPT 审中-公开
    迭代写序列中断

    公开(公告)号：WO2017086925A1

    公开(公告)日：2017-05-26

    申请号：PCT/US2015/061009

    申请日：2015-11-17

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： LESARTRE, Gregg B. ,  FOLTIN, Martin

    IPC: G06F13/16 ,  G06F13/24 ,  G06F12/00

    CPC classification number: G06F13/1668 ,  G06F13/16 ,  G06F13/24

    Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.

    Abstract translation:

    示例实现涉及内存读取请求。 例如，实现可以包括跟踪迭代写入序列的进展以将数据写入到存储器模块的存储器元件。 检测到接收到的读取请求被寻址到包括正在经历迭代写入序列的存储器元件的存储体。 基于追踪的进度，确定时间以插入读取请求来中断迭代写入序列。 在预定的读取延迟内返回迭代写入序列和数据的操作之间的时间对准。

    MAPPING RESISTANCE LEVEL STATES TO MULTI-BIT DATA VALUES
    12.
    发明申请
    MAPPING RESISTANCE LEVEL STATES TO MULTI-BIT DATA VALUES 审中-公开
    映射电阻状态到多位数据值

    公开(公告)号：WO2017026998A1

    公开(公告)日：2017-02-16

    申请号：PCT/US2015/044338

    申请日：2015-08-07

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： LESARTRE, Gregg B.

    IPC: G11C13/00 ,  G11C11/15

    CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2213/77

    Abstract: An example device in accordance with an aspect of the present disclosure includes a controller to map a plurality of resistance level states, of a multilevel memory device of a cross point memory array, to a corresponding plurality of multi-bit data values according to a selected gray code. The modified gray code involves adjacent data values differing by no more than one bit value, groups more common data values together, starts with a first data value whose bit values are all zeroes, and ends with a last data value whose bit values are all ones.

    Abstract translation: 根据本公开的一个方面的示例性装置包括控制器，用于根据所选择的将多个存储器阵列的多电平存储器件的多个电阻状态映射到相应的多个多位数据值 灰色代码。 经修改的灰度码涉及到不同于一个比特值的相邻数据值，将更多的公共数据值组合在一起，以比特值全为零的第一数据值开始，并以比特值全为零的最后数据值结束 。

    MEDIA CONTROLLER WITH COORDINATION BUFFER
    13.
    发明申请
    MEDIA CONTROLLER WITH COORDINATION BUFFER 审中-公开
    媒体控制器与协调缓冲区

    公开(公告)号：WO2016068870A1

    公开(公告)日：2016-05-06

    申请号：PCT/US2014/062593

    申请日：2014-10-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： SPRAGUE, Fred A. ,  LESARTRE, Gregg B.

    IPC: G06F13/14 ,  G06F12/06

    CPC classification number: G06F12/084 ,  G06F12/082 ,  G06F13/14

    Abstract: A system includes a media controller to control data access from a set of computing nodes to a shared memory. A coordination buffer holds data update requests generated from the set of computing nodes to the media controller. The media controller enables data in the shared memory to be modified in accordance with the data update requests based on a comparison of the data update requests in the coordination buffer.

    Abstract translation: 系统包括媒体控制器，用于控制从一组计算节点到共享存储器的数据访问。 协调缓冲器将从该组计算节点生成的数据更新请求保存到媒体控制器。 基于协调缓冲器中的数据更新请求的比较，媒体控制器使得根据数据更新请求修改共享存储器中的数据。

    SERDES LINK MANAGEMENT
    16.
    发明申请
    SERDES LINK MANAGEMENT 审中-公开
    SERDES LINK管理

    公开(公告)号：WO2017027028A1

    公开(公告)日：2017-02-16

    申请号：PCT/US2015/044849

    申请日：2015-08-12

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： AKKERMAN, Ryan ,  LESARTRE, Gregg B. ,  REGAN, James Donald

    IPC: G06F11/10 ,  G06F13/16

    CPC classification number: G06F11/1004

    Abstract: A memory device includes a serializer-deserializer (SERDES) link controller that receives a flit of data associated with a transaction across a SERDES link. The SERDES link controller forwards the flit of data to a next SERDES hop before completing a cyclical redundancy check (CRC) on a superflit. The superflit includes the flit of data. The SERDES link controller forwards the flit of data to a memory interface before completing the CRC, if a memory address of the transaction matches a memory address associated with the SERDES link controller. Additionally, the SERDES link forwards a result of the CRC to the memory interface.

    Abstract translation: 存储器件包括串行器 - 解串器（SERDES）链接控制器，其通过SERDES链接接收与事务相关联的数据。 SERDES链路控制器将flit数据转发到下一个SERDES跳，然后再在superflit上完成循环冗余校验（CRC）。 超级包含数据的闪烁。 如果事务的存储器地址与SERDES链路控制器相关联的存储器地址匹配，则SERDES链路控制器将完成CRC之前的数据转发到存储器接口。 此外，SERDES链路将CRC的结果转发到存储器接口。

    DATA BLOCK WRITE MAPPED TO MEMORY BANK
    17.
    发明申请
    DATA BLOCK WRITE MAPPED TO MEMORY BANK 审中-公开
    数据块写入映射到存储器银行

    公开(公告)号：WO2016195704A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2015/034375

    申请日：2015-06-05

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BALASUBRAMONIAN, Rajeev ,  LESARTRE, Gregg B. ,  SCHREIBER, Robert ,  MURALIMANOHAR, Naveen

    IPC: G06F12/06

    CPC classification number: H04N19/00 ,  G06F12/023 ,  G06F2212/1044 ,  G06F2212/401 ,  G06T9/00

    Abstract: Techniques for data block write mapped to memory bank are provided. In one aspect, a block of data to be written to a line in a bank of a rank of memory may be received. The rank of memory may comprise multiple banks, and the block of data may be written to a number of memory devices determined by the size of the data block. A memory device mapping may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. It may be determined when the banks of the memory devices used to store the line are available for writing. The block of data may be written to the banks of the memory devices when the banks are available for writing.

    Abstract translation: 提供了映射到存储体的数据块写入技术。 在一个方面，可以接收要写入存储器等级的存储体中的行的数据块。 存储器的等级可以包括多个存储体，并且数据块可以写入由数据块的大小确定的多个存储器件。 可以检索存储器设备映射。 映射可以确定将数据块写入等级内的存储器件的顺序。 用于存储线路的存储器件的存储体可用于写入。 当银行可用于写入时，数据块可以被写入存储器件的存储体。

    COMPRESSED DATA BLOCK MAPPING
    18.
    发明申请
    COMPRESSED DATA BLOCK MAPPING 审中-公开
    压缩数据块映射

    公开(公告)号：WO2016195702A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2015/034368

    申请日：2015-06-05

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BALASUBRAMONIAN, Rajeev ,  LESARTRE, Gregg B. ,  SCHREIBER, Robert ,  MURALIMANOHAR, Naveen

    IPC: G06F12/06

    CPC classification number: G06F12/023 ,  G06F2212/1044 ,  G06F2212/401 ,  G06T9/00 ,  H04N19/00

    Abstract: Techniques for compressed data block mapping are provided. In one aspect, a request to retrieve a block of data stored in memory devices in a rank of memory may be received. The mapping that was used when the data block was stored may be determined. The retrieved data block may be ordered based on the determined mapping. The block of data may be decompressed.

    Abstract translation: 提供了压缩数据块映射技术。 在一个方面，可以接收到检索存储在存储器等级的存储器件中的数据块的请求。 可以确定在存储数据块时使用的映射。 所检索的数据块可以基于所确定的映射来排序。 数据块可以被解压缩。

    A MULTI-TIER SECURITY FRAMEWORK
    19.
    发明申请
    A MULTI-TIER SECURITY FRAMEWORK 审中-公开
    多层次的安全框架

    公开(公告)号：WO2016093813A1

    公开(公告)日：2016-06-16

    申请号：PCT/US2014/069458

    申请日：2014-12-10

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： HERRELL, Russ W. ,  LESARTRE, Gregg B. ,  ASTFALK, Greg ,  VOIGT, Douglas L.

    IPC: G06F21/79

    CPC classification number: G06F21/79 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/1491 ,  G06F21/6218 ,  G06F2212/1052

    Abstract: A security framework for a multi-tenant, multi-tier computer system with embedded processing is described. A multi-tenant security framework is created for a combined processing and storage hierarchy of multiple tiers. The multi-tenant security framework is applied to multiple execution levels of the memory device. The multi-tenant security framework is applied to multiple layers of application server software of the memory device. The multi-tenant security framework is also applied to multiple layers of storage server software of the memory device.

    Abstract translation: 描述了具有嵌入式处理的多租户多层计算机系统的安全框架。 为多层次的组合处理和存储层次结构创建多租户安全框架。 多租户安全框架被应用于存储设备的多个执行级别。 多租户安全框架应用于存储设备的多层应用服务器软件。 多租户安全框架也适用于存储设备的多层存储服务器软件。

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