公开(公告)号：WO2017023252A1

公开(公告)日：2017-02-09

申请号：PCT/US2015/043165

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DAGLIS, Alexandros ,  FARABOSCHI, Paolo ,  CAI, Qiong ,  GOSTIN, Gary

IPC: G06F12/08 ,  G06F12/06

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/502

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

Abstract translation: 一种技术包括响应于与多个处理节点的给定处理节点发生的高速缓存未命中，使用用于多个处理节点的基于目录的一致性系统来调节与高速缓存未命中相关联的地址的窥探。 使用基于目录的一致性系统来调节地址是否包含在窥探域中至少部分地基于与地址相关联的多个高速缓存未命中。

公开(公告)号：WO2017019095A1

公开(公告)日：2017-02-02

申请号：PCT/US2015/042953

申请日：2015-07-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： LILLIBRIDGE, Mark David ,  GOSTIN, Gary ,  FARABOSCHI, Paolo ,  SHERLOCK, Derek Alan ,  RAY, Harvey

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0607 ,  G06F2212/1016

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

Abstract translation: 在一些示例中，多个处理器的每个处理器应用交织变换来执行多个存储体的交织访问，其中对于多个处理器使用的任何给定存储器地址，应用任何交织变换导致选择 多个存储器组中的相同存储体和相同存储体内相同的地址。

公开(公告)号：WO2019209328A1

公开(公告)日：2019-10-31

申请号：PCT/US2018/029885

申请日：2018-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： MCDONALD, Nicolas ,  GOSTIN, Gary ,  DAVIS, Alan

IPC: H04L12/931 ,  H04L12/935

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

公开(公告)号：WO2017018976A1

公开(公告)日：2017-02-02

申请号：PCT/US2015/041883

申请日：2015-07-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： SHERLOCK, Derek Alan ,  GOSTIN, Gary

IPC: G06F21/00 ,  G06F21/70

CPC classification number: G06F9/52 ,  G06F2209/522

Abstract: In some examples, a lock manager may receive a lock release message from a processor. The lock release message may identify a lock that synchronizes control of a shared resource. The lock manager may determine, for the lock identified in the lock release message, multiple processors contending to acquire the lock and select a particular processor among the multiple processors to acquire the lock.

Abstract translation: 在一些示例中，锁管理器可以从处理器接收锁释放消息。 锁定释放消息可以标识同步对共享资源的控制的锁。 锁定管理器可以针对锁定释放消息中识别的锁来确定多个处理器，其中，争夺获取锁定并在多个处理器中选择特定处理器以获取锁定。

公开(公告)号：WO2019212461A1

公开(公告)日：2019-11-07

申请号：PCT/US2018/030111

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： MCDONALD, Nicolas ,  GOSTIN, Gary ,  DAVIS, Alan

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/931 ,  H04L12/42

Abstract: A co-packaged, multiplane network includes: an enclosure; a portion of a first network plane disposed within the enclosure and comprising a first plurality of interconnected switches; a portion of a second network plane disposed within the enclosure and comprising a second plurality of interconnected switches, the second network plane being independent of the first network plane and having the same topology as the first network plane; and a plurality of connectors, each connector being communicatively coupled to a respective port of each of the first plurality of interconnected switches and the second plurality of interconnected switches.

公开(公告)号：WO2018217960A1

公开(公告)日：2018-11-29

申请号：PCT/US2018/034242

申请日：2018-05-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： MCDONALD, Nicholas George ,  GOSTIN, Gary ,  EMMOT, Darel N ,  LESARTRE, Gregg B ,  DAVIS, Al ,  SHERLOCK, Derek Alan

IPC: H04L12/935

Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.

公开(公告)号：WO2016036347A1

公开(公告)日：2016-03-10

申请号：PCT/US2014/053704

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： RAY, Harvey ,  GOSTIN, Gary ,  SHERLOCK, Derek Alan ,  LESARTRE, Gregg B.

IPC: G06F11/10 ,  G06F12/00

CPC classification number: G06F3/0637 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0644 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/52 ,  G06F11/108

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

Abstract translation: 根据一个示例，第一冗余控制器可以从奇偶校验媒体控制器请求锁，以执行访问条带中的多个存储器模块的第一序列。 可以为条纹获取锁定，使得可以在条纹上执行第一序列。 然后可以从条带中释放锁。

公开(公告)号：EP2810176B1

公开(公告)日：2016-12-07

申请号：EP12867410.8

申请日：2012-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： GOSTIN, Gary ,  HANDGEN, Erin

IPC: G06F13/16 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1666 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0683 ,  G06F11/1064 ,  G06F11/1068 ,  G11C29/808

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be 'accessed in both single and double chip spare modes.

公开(公告)号：EP3014448A1

公开(公告)日：2016-05-04

申请号：EP13887761.8

申请日：2013-06-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： LESARTRE, Gregg B. ,  MORRIS, Dale C. ,  GOSTIN, Gary ,  HERRELL, Russ W. ,  WHEELER, Andrew R. ,  GAITHER, Blaine D.

IPC: G06F11/07

CPC classification number: G06F11/1666 ,  G06F11/1004 ,  G06F11/108 ,  G06F11/20 ,  G06F11/2069 ,  G06F2201/805

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

公开(公告)号：EP2764439B1

公开(公告)日：2019-06-26

申请号：EP11873708.9

申请日：2011-10-07

Applicant: Hewlett Packard Enterprise Development LP

Inventor： GOSTIN, Gary ,  WARNER, Craig ,  BOCKHAUS, John W.

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0873 ,  G06F12/10 ,  G06F13/16 ,  G06F12/06