公开(公告)号：EP3952106A2

公开(公告)日：2022-02-09

申请号：EP21176396.6

申请日：2015-01-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： SHAHMOHAMMADI, Mina ,  BABAIE, Masoud ,  STASZEWSKI, Robert

IPC: H03B5/12

Abstract: The invention relates to a resonator circuit (100), the resonator circuit (100) comprising a transformer (101) comprising a primary winding (103) and a secondary winding (105), wherein the primary winding (103) is inductively coupled with the secondary winding (105), a primary capacitor (107) being connected to the primary winding (103), the primary capacitor (107) and the primary winding (103) forming a primary circuit, and a secondary capacitor (109) being connected to the secondary winding (105), the secondary capacitor (109) and the secondary winding (105) forming a secondary circuit, wherein the resonator circuit (100) has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit (100) has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.

公开(公告)号：EP3243207A1

公开(公告)日：2017-11-15

申请号：EP15701042.2

申请日：2015-01-27

Applicant: Huawei Technologies Co. Ltd.

Inventor： QIAN, Huizhen ,  LUO, Xun ,  STASZEWSKI, Robert

IPC: H01F27/28 ,  H01F19/08 ,  H03F1/08 ,  H03F1/22

CPC classification number: H03F1/223 ,  H01F19/08 ,  H01F27/2804 ,  H01F2019/085 ,  H01F2027/2809 ,  H01F2027/2819 ,  H03F1/086 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2173 ,  H03F3/245 ,  H03F2200/09 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03H7/38 ,  H03H7/42

Abstract: A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances.

公开(公告)号：EP3158406A1

公开(公告)日：2017-04-26

申请号：EP15702273.2

申请日：2015-02-03

Applicant: Huawei Technologies Co. Ltd.

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50

CPC classification number: G04F10/005 ,  H03M3/414

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

Abstract translation: 时间 - 数字转换器（300,400）包括：用于接收时域输入信号（Tin）的输入（302,402）; 输出（306,406），用于提供数字输出信号（Dout）; 时间寄存器（305,405），其耦合到所述输入（302,403）并且耦合到第一节点（308,408）; 耦合到所述时间寄存器（305,405）的时间量化器（307,407），用于在所述输出（306,406）处提供所述数字输出信号（Dout）; 以及耦合到所述输出（306,406）用于在所述第一节点（308,408）处提供反馈信号（E，Qerr）的数字到时间转换器（309,409）。

公开(公告)号：EP3502804B1

公开(公告)日：2020-07-22

申请号：EP18193113.0

申请日：2015-02-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50 ,  H03M3/00

公开(公告)号：EP3149546B1

公开(公告)日：2019-04-10

申请号：EP15704250.8

申请日：2015-02-03

Applicant: Huawei Technologies Co. Ltd.

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50 ,  H03K5/135

公开(公告)号：EP3149546A1

公开(公告)日：2017-04-05

申请号：EP15704250.8

申请日：2015-02-03

Applicant: Huawei Technologies Co. Ltd.

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50

CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

Abstract translation: 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 用于产生一对电平信号（VC1，VC2）的一对三态反相器（301,302）; 以及耦合到所述电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中所述三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。