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    TIME REGISTER
    1.
    发明申请
    TIME REGISTER 审中-公开
    时间注册

    公开(公告)号：WO2016124227A1

    公开(公告)日：2016-08-11

    申请号：PCT/EP2015/052187

    申请日：2015-02-03

    Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M1/50

    CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

    Abstract: A time register (300) includes: a pair of inputs (345, 346) coupled to a pair of input clocks (IN 1 , IN 2 ); a pair of tri-state inverters (301, 302) for producing a pair of level signals (V C1 , V C2 ); and a pair of outputs (347, 348) coupled to the level signals (V C1 , V C2 ) for producing a pair of output clocks (OUT 1 , OUT 2 ), wherein the tri-state inverters (301, 302) are responsive to a pair of state signals (S 1 , S 2 ) and the pair of input clocks (IN 1 , IN 2 ) for holding or discharging the level signals (V C1 , V C2 ).

    Abstract translation: 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 一对用于产生一对电平信号（VC1，VC2）的三态反相器（301,302）; 以及耦合到电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。

    TIME-TO-DIGITAL CONVERTER
    2.
    发明申请
    TIME-TO-DIGITAL CONVERTER 审中-公开
    时间到数字转换器

    公开(公告)号：WO2016124226A1

    公开(公告)日：2016-08-11

    申请号：PCT/EP2015/052183

    申请日：2015-02-03

    Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M1/50

    CPC classification number: G04F10/005 ,  H03M3/414

    Abstract: A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Q err ) at the first node (308, 408).

    Abstract translation: 时间数字转换器（300,400）包括：用于接收时域输入信号（Tin）的输入端（302,402）; 用于提供数字输出信号（Dout）的输出（306,406）; 耦合到输入（302,403）和第一节点（308,408）的时间寄存器（305,405）; 耦合到时间寄存器（305,405）的时间量化器（307,407），用于在输出端（306,406）处提供数字输出信号（Dout）; 以及耦合到所述输出（306,406）的数字 - 时间转换器（309,409），用于在所述第一节点（308,408）处提供反馈信号（E，Qerr）。

    TIME-TO-DIGITAL CONVERTER
    3.
    发明公开
    TIME-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：EP3502804A1

    公开(公告)日：2019-06-26

    申请号：EP18193113.0

    申请日：2015-02-03

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M1/50 ,  H03M3/00

    Abstract: A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time-domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Q err ) at the first node (308, 408).

    TIME-TO-DIGITAL CONVERTER
    4.
    发明授权
    TIME-TO-DIGITAL CONVERTER 有权

    公开(公告)号：EP3158406B1

    公开(公告)日：2018-10-03

    申请号：EP15702273.2

    申请日：2015-02-03

    Applicant: Huawei Technologies Co. Ltd.

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M3/00

    CPC classification number: G04F10/005 ,  H03M3/414

    Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

    TIME-TO-DIGITAL CONVERTER
    5.
    发明公开
    TIME-TO-DIGITAL CONVERTER 审中-公开
    时间数字转换器

    公开(公告)号：EP3158406A1

    公开(公告)日：2017-04-26

    申请号：EP15702273.2

    申请日：2015-02-03

    Applicant: Huawei Technologies Co. Ltd.

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M1/50

    CPC classification number: G04F10/005 ,  H03M3/414

    Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

    Abstract translation: 时间 - 数字转换器（300,400）包括：用于接收时域输入信号（Tin）的输入（302,402）; 输出（306,406），用于提供数字输出信号（Dout）; 时间寄存器（305,405），其耦合到所述输入（302,403）并且耦合到第一节点（308,408）; 耦合到所述时间寄存器（305,405）的时间量化器（307,407），用于在所述输出（306,406）处提供所述数字输出信号（Dout）; 以及耦合到所述输出（306,406）用于在所述第一节点（308,408）处提供反馈信号（E，Qerr）的数字到时间转换器（309,409）。

    LOGIC GATE CIRCUIT, LATCH, AND TRIGGER
    6.
    发明公开
    LOGIC GATE CIRCUIT, LATCH, AND TRIGGER 审中-实审

    公开(公告)号：EP4383574A1

    公开(公告)日：2024-06-12

    申请号：EP21959729.1

    申请日：2021-10-09

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： WU, Ying ,  JING, Weiliang ,  HOU, Zhaozhao ,  FAN, Renshi ,  XU, Jeffrey

    IPC: H03K19/20

    CPC classification number: H03K19/20

    Abstract: This application provides a logic gate circuit, a latch, and a flip-flop, relates to the field of logic circuits, and provides a logic gate circuit that is based on an NFET. The logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first NFET. The first NFET includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.

    TIME REGISTER
    10.
    发明公开
    TIME REGISTER 审中-公开
    ZEITREGISTER

    公开(公告)号：EP3149546A1

    公开(公告)日：2017-04-05

    申请号：EP15704250.8

    申请日：2015-02-03

    Applicant: Huawei Technologies Co. Ltd.

    Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC: G04F10/00 ,  H03M1/50

    CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

    Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

    Abstract translation: 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 用于产生一对电平信号（VC1，VC2）的一对三态反相器（301,302）; 以及耦合到所述电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中所述三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。

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