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公开(公告)号：DE69223508D1
公开(公告)日：1998-01-22
申请号：DE69223508
申请日：1992-07-10
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
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公开(公告)号：DE69118372T2
公开(公告)日：1996-11-14
申请号：DE69118372
申请日：1991-07-17
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
Abstract: A Decimation filter for converting a train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples in accordance with the formula The decimation filter comprises means for computing one PCM sample from a sequence of 1 sigma-delta samples in synchronism with a PCM clock. and also means for determining whether a phase correction has to be introduced in said PCM clock in order to lock the generation of the PCM samples on the receive clock extracted from the received signal. From the latter determination, the decimation filter has means (410, 311, 411, 312, 412, 313) which shifts the computation process of the sequence of at least one sigma-delta clock pulse in order to provide a phase control of the generation of the PCM samples. In a preferred embodiment, the value of p is equal to 3 and the filter includes computing means (350, 360, 370) for computing one PCM sample from a sequence of 3xN input samples according to the formula: where C(n) is the sequence of the coefficients of the decimation filter corresponding to a determined decimation factor N. The filter further includes - means (321, 327, 331, 337, 341, 347) for generating the sequence C(n) corresponding to a determined decimation factor N, and multiplying means (323, 333, 343) for multiplying each coefficient C(n) of said sequence by a sigma-delta input sample S(i+n). The filter detects the occurence of the coefficient C(2xN-1) which is equal to zero and includes means (311, 312, 313) responsive to the detection of said coefficient C(2xN-1) for shifting of one sigma-delta clock pulse the initiating of the computing process of the next PCM pulse in order to provide a phase control of the generation of the PCM samples.
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公开(公告)号：DE69118372D1
公开(公告)日：1996-05-02
申请号：DE69118372
申请日：1991-07-17
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
Abstract: A Decimation filter for converting a train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples in accordance with the formula The decimation filter comprises means for computing one PCM sample from a sequence of 1 sigma-delta samples in synchronism with a PCM clock. and also means for determining whether a phase correction has to be introduced in said PCM clock in order to lock the generation of the PCM samples on the receive clock extracted from the received signal. From the latter determination, the decimation filter has means (410, 311, 411, 312, 412, 313) which shifts the computation process of the sequence of at least one sigma-delta clock pulse in order to provide a phase control of the generation of the PCM samples. In a preferred embodiment, the value of p is equal to 3 and the filter includes computing means (350, 360, 370) for computing one PCM sample from a sequence of 3xN input samples according to the formula: where C(n) is the sequence of the coefficients of the decimation filter corresponding to a determined decimation factor N. The filter further includes - means (321, 327, 331, 337, 341, 347) for generating the sequence C(n) corresponding to a determined decimation factor N, and multiplying means (323, 333, 343) for multiplying each coefficient C(n) of said sequence by a sigma-delta input sample S(i+n). The filter detects the occurence of the coefficient C(2xN-1) which is equal to zero and includes means (311, 312, 313) responsive to the detection of said coefficient C(2xN-1) for shifting of one sigma-delta clock pulse the initiating of the computing process of the next PCM pulse in order to provide a phase control of the generation of the PCM samples.
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公开(公告)号：CA1286000C
公开(公告)日：1991-07-09
申请号：CA576316
申请日：1988-09-01
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATICK , LALLEMAND ERIC
Abstract: Predictive clock extracting circuit which having means for determining the duration between two consecutive transitions of a multilevel digital signal, and means for generating a pulse SPL at half the said duration after a the transition following on two consecutive previous transitions. A phase locked oscillator driven by said SPL pulse generates the extracted clock signal, in phase with pulse SPL and which coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs, the result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. A divide by 2 circuit divides the result N(i) stored into the first counter at second transition. The preferred embodiment of the invention also involves an an up/down counter which generates a second counter K that is expected to be representative of half the value of the first counter N(i). This second counter K is used to generate the extracted clock in phase with the middle of the eye intervals. Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor. A comparator comparing K(i) and N(i)/2 controls the update of the current value K(i) according the following rules. if the value K(i) is superior to N(i)/2 at the second transition, then the counter K is updated by decrementing its current value. Conversely, when N(i) is inferior to N(i)/2, then counter K is updated by incrementing its current value. In this way, the extracted clock which will be derived from counter K varies slowly and integrates sudden variations of the content of the first counter N. A counter P initialized with the updated value K(i+l) of counter K starts running from K(i+l) to zero in response to the detection of the transition following on two said first and second transition and delivers a pulse SPL whenever its content reaches the value zero. The phase locked oscillator controlled by the pulse SPL generates the extracted clock which is likely to coincide with the middle of the eye pattern.
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