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公开(公告)号：DE3169628D1
公开(公告)日：1985-05-02
申请号：DE3169628
申请日：1981-12-29
Applicant: IBM , IBM FRANCE
Inventor： ABBIATE JEAN-CLAUDE
Abstract: An interface device for synchronizing an internally clocked modem and data terminal equipment (DTE) provided with their own clock circuits, each of said own terminal clock circuit providing an external clock signal (RC Ext). The interface includes a PLO generating a recovered clock signal (XCO). At a moment defined by a request to send signal the phases of XCO and RC Ext are compared with each other and a switched clock signal SWC oscillating at a fast rate for a time interval corresponding to the phase delay between RC Ext and XCO and subsequently oscillating at a slow rate, is generated. The signal SWC is used for shifting RC Ext and terminal provided data RD Ext into shift registers respectively. The shifted RC Ext is used for controlling the adjustment of the interface PLO.
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公开(公告)号：DE69027531D1
公开(公告)日：1996-07-25
申请号：DE69027531
申请日：1990-09-28
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , UNGERBOECK GOTTFRIED DR , BLANC ALAIN
Abstract: Data circuit terminating equipment DCE (100) which allows the connection of a Data terminal equipment DTE (63) to a telecommunication line and which includes timing arrangements circuits for particularly providing the DTE with transmitter signal element timing (114) and receiver signal element timing (115). The DCE includes processing means (61) for computing a sequence of digital values A(n) and means (60, 23, 22) for deriving from said sequence of digital values A(n) a corresponding sequence of interrupt signals T(n). The DCE further includes timing arrangement circuits (69, 70, 71) for generating a set of N timing pulses at the nominal rate on the occurrence of one interrupt signal T(n). By controlling the generation of the sequence of digital values, the processing means (61) can control the frequency, the phase of every clock generated by the timing arrangements circuits. The receiver signal element timing, the transmitter signal element timing the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are controlled by different sequence of digital values computed by the processing means. By generating appropriate sequences of digital values, the processing means can provide any relationship between the different clocks: a transmit signal element timing being slaved on the receiver signal element timing in a synchronous mode, on an external clock in a tailing mode. The timing arrangement circuits can also provide a transmit sampling clock slaved on the receive sampling clock in order to perform powerful digital echo cancellation techniques. More generally, the processing means (61) can provide any relationship between two determined clocks. Moreover, the DCE including a DTE receive interface circuit 21 transmitting a set of N receive data at the nominal receive clock rate and maintaining the N data bit until the next interrupt signal, the processing means can control the length of the Nth bit, which when a STOP bit can allow the compensation of the DTE and the line data throughput difference.
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公开(公告)号：DE69120924D1
公开(公告)日：1996-08-22
申请号：DE69120924
申请日：1991-01-15
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , RICHTER GERARD
Abstract: Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal by means of at least one feedback loop. The sigma-delta converter further includes means (221, 222) located in said at least feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the thresholds device. That results in an increase of the signal-to-noise ratio and the linearity of the converter allowing the manufacture of a sigma-delta convertors with discrete components without requiring the development of an integrated circuit using switched capacitor technology.
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公开(公告)号：DE69022411D1
公开(公告)日：1995-10-19
申请号：DE69022411
申请日：1990-06-29
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , QUENEL LUCIEN
Abstract: A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises well-known means for generating Analog Carrier Detect (ACD) DCE internal signal (ACD is 'up' if energy is detected on the DCE receive line), as well as Analog Squared Data (ASD) DCE internal signal (each ASD square pulse corresponds to a positive or a negative pulse on the DCE receive line), and ASD WIDTH ERROR DCE internal signal (ASD WIDTH ERROR is 'up' anytime an ASD square pulse is found to have either a too little or too large width), from the flow of data transmitted by the network and received on DCE receive line. The system also comprises new means for generating Lack of Receiver Timing (LRT) DCE internal signal (LRT is 'up' if there is a lack of a certain number of ASD square pulses within a given time), Block Error ASD (BEASD) DCE internal signal (BEASD is 'up' if so many ASD WIDTH ERROR pulses are counted within a given time), and Block Error Bipolar (BEBIP) DCE internal signal (BEBIP is 'up' if so many bipolar violations at the network interface, are detected within a given time). Finally, the system includes a logical decision process, which leads the DCE to automatically adjust its functional speed to the rate of data transmitted by the network and received on DCE receive line (step 710). The process consists in setting the DCE to the highest possible functional speed (step 701), and for that particular speed, checking all four of ACD (step 702), LRT (step 707), BEASD (step 708) and BEBIP (step 709) DCE internal signals; if one of the checkings is not satisfactory, setting the DCE to the next possible lower speed (step 704), or if all checkings are satisfactory, stopping the process as the DCE is ready to work (step 710).
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公开(公告)号：DE69114129T2
公开(公告)日：1996-06-13
申请号：DE69114129
申请日：1991-07-17
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , ORENGO GERARD , RICHTER GERARD
Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.
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Patent Agency Ranking
公开(公告)号：DE69114129D1
公开(公告)日：1995-11-30
申请号：DE69114129
申请日：1991-07-17
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , ORENGO GERARD , RICHTER GERARD
Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.
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公开(公告)号：DE3783915D1
公开(公告)日：1993-03-11
申请号：DE3783915
申请日：1987-10-19
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , LALLEMAND ERIC
Abstract: An eye opening time measuring block includes a counter controlled by an analog squared signal derived from the data flow on the line. A division by two is effected to determine the best sampling time. A counter is set running in response to the first transition of the multilevel digital signal and is halted at a second transition of the signal. The divide-by-two circuit divides the interval determined between the first and second transitions of the signal by two. The result is applied to a phase locked oscillator (124) which generates a sampling clock with the middle of the eye of the analog squared wave signal.
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公开(公告)号：DE69223508T2
公开(公告)日：1998-06-25
申请号：DE69223508
申请日：1992-07-10
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
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公开(公告)号：DE69120924T2
公开(公告)日：1997-01-30
申请号：DE69120924
申请日：1991-01-15
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , RICHTER GERARD
Abstract: Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal by means of at least one feedback loop. The sigma-delta converter further includes means (221, 222) located in said at least feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the thresholds device. That results in an increase of the signal-to-noise ratio and the linearity of the converter allowing the manufacture of a sigma-delta convertors with discrete components without requiring the development of an integrated circuit using switched capacitor technology.
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公开(公告)号：DE3783915T2
公开(公告)日：1993-08-19
申请号：DE3783915
申请日：1987-10-19
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , LALLEMAND ERIC
Abstract: Predictive clock extracting circuit which having means for determining the duration between two consecutive transitions of a multilevel digital signal, and means for generating a pulse SPL at half the said duration after a the transition following on two consecutive previous transitions. A phase locked oscillator (23) driven by said SPL pulse generates the extracted clock signal, in phase with pulse SPL and which coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N (20) which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs, the result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. A divide by 2 circuit (21) divides the result N(i) stored into the first counter at second transition. The preferred embodiment of the invention also involves an an up/down counter which generates a second counter K that is expected to be representative of half the value of the first counter N(i). This second counter K is used to generate the extracted clock in phase with the middle of the eye intervals. Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor. A comparator comparing K(i) and N(i)/2 controls the update of the current value K(i) according the following rules. if the value K(i) is superior to N(i)/2 at the second transition, then the counter K is updated by decrementing its current value. Conversely, when N(i) is inferior to N(i)/2, then counter K is updated by incrementing its current value. In this way, the extracted clock which will be derived from counter K varies slowly and integrates sudden variations of the content of the first counter N. A counter P (22) initialized with the updated value K(i+1) of counter K starts running from K(i+1) to zero in response to the detection of the transition following on two said first and second transition and delivers a pulse SPL whenever its content reaches the value zero. The phase locked oscillator (23) controlled by the pulse SPL generates the extracted clock which is likely to coincide with the middle of the eye pattern.
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