公开(公告)号：DE3789726D1

公开(公告)日：1994-06-09

申请号：DE3789726

申请日：1987-02-17

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  FURMAN ANATOL

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/412 ,  G11C8/00

Abstract: A memory cell that allows simultaneous writing into the cell and reading from the cell includes a cross-coupled latch (10) in which two pairs of a load transistor (12, 14) and a pull-down transistor (20, 24) are connected at respective first and second coupling points (16, 18). However, the feedback path from the first coupling point (16) to the gate electrode of the pull-down transistor (24) of the other pair passes through a feedback transistor (30) which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals (WP1, WP2) can be impressed upon the gate electrode of the thus separated pull down transistor (24). Simultaneously, the signal on the first coupling point (16) can be selectively impressed upon any combination of a plurality of read lines (58, 60, 62). If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.

公开(公告)号：DE3476600D1

公开(公告)日：1989-03-09

申请号：DE3476600

申请日：1984-05-03

Applicant: IBM

Inventor： BERNSTEIN KERRY

IPC: G11C11/41 ,  G11C8/16 ,  G11C8/20 ,  G11C11/413 ,  G11C11/417 ,  G11C8/00

Abstract: The present invention is especially directed towards an improved means (24-26) for comparing the address inputs (P1-P3) of word decoders (12-14) in a memory array (10) such that, when a compare occurs, selected ones (13 and/or 14) of the array word decoders are disabled to prevent a multiple read of identical cells (11), and selected higher order read heads (22 and/or 23) are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder. The comparator circuit (24,25, 26) employs a ripple effect and comprises a plurality of exclusive-OR circuits (69, 69a, 69b) interposed with source follower circuits (72,73). Each of the first and last steps of the comparator is an exclusive-OR circuit. The comparator circuit is extendable to any size system and results in better power performance as well as a smaller size of the array.

公开(公告)号：DE3786478T2

公开(公告)日：1994-02-17

申请号：DE3786478

申请日：1987-02-27

Applicant: IBM

Inventor： BERNSTEIN KERRY

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/401 ,  G11C11/419 ,  G11C8/00

Abstract: Read circuit for a memory system having multiple read ports (RP1, RP2, RP3). Bit lines (46, 48, 50) are precharged. In a reading operation, the recharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches (52, 54. 56), associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals (P1, P2, P3).

公开(公告)号：DE3786478D1

公开(公告)日：1993-08-19

申请号：DE3786478

申请日：1987-02-27

Applicant: IBM

Inventor： BERNSTEIN KERRY

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/401 ,  G11C11/419 ,  G11C8/00

Abstract: Read circuit for a memory system having multiple read ports (RP1, RP2, RP3). Bit lines (46, 48, 50) are precharged. In a reading operation, the recharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches (52, 54. 56), associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals (P1, P2, P3).

公开(公告)号：DE3479616D1

公开(公告)日：1989-10-05

申请号：DE3479616

申请日：1984-05-09

Applicant: IBM

Inventor： BERNSTEIN KERRY

IPC: G11C11/417 ,  G11C7/00 ,  G11C8/16 ,  G11C8/18 ,  G11C8/20 ,  G11C11/41 ,  G11C8/00

Abstract: The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are altered, i.e., inhibited from reading the output data of the higher order bit lines and forced to read or copy the lowest order bit lines having the same address as the uninhibited word decoder.