公开(公告)号：US3700922A

公开(公告)日：1972-10-24

申请号：US3700922D

申请日：1970-09-21

Applicant: IBM

Inventor： FURMAN ANATOL

IPC: H03K17/042 ,  H03K17/60

CPC classification number: H03K17/04213

Abstract: A transistorized power gating circuit for providing a positive pull down of the capacitive load which derives from the load, via a feedback loop, the turn-off drive voltage required to discharge the capacitive load which drive voltage disappears as the load capacitance discharges. The circuit obviates the need of a continuous current flow to initiate the device used in discharging the load capacitance and eliminates the attendent turn-on delays associated with disabling direct coupled pull down circuits.

Abstract translation: 晶体管功率门控电路，用于提供电容性负载的正下拉，该负载通过反馈回路从负载导出，以便在负载电容放电时驱动电压消耗所需的放电容性负载所需的关断驱动电压。 该电路消除了连续电流流动的需要，以启动用于放电负载电容的装置，并消除与禁用直接耦合下拉电路相关联的出现的导通延迟。

公开(公告)号：IT1150088B

公开(公告)日：1986-12-10

申请号：IT2040680

申请日：1980-03-07

Applicant: IBM

Inventor： FURMAN ANATOL

IPC: G11C11/41 ,  G11C11/416 ,  H03K5/02 ,  H03K5/08 ,  H03F

公开(公告)号：DE2642303A1

公开(公告)日：1977-04-07

申请号：DE2642303

申请日：1976-09-21

Applicant: IBM

Inventor： FURMAN ANATOL ,  KALTER HOWARD LEO ,  NAGEL JOHANN WERNER

IPC: H01L27/10 ,  G11C11/24 ,  G11C11/35 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/07 ,  H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L29/76

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

公开(公告)号：DE3789726D1

公开(公告)日：1994-06-09

申请号：DE3789726

申请日：1987-02-17

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  FURMAN ANATOL

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/412 ,  G11C8/00

Abstract: A memory cell that allows simultaneous writing into the cell and reading from the cell includes a cross-coupled latch (10) in which two pairs of a load transistor (12, 14) and a pull-down transistor (20, 24) are connected at respective first and second coupling points (16, 18). However, the feedback path from the first coupling point (16) to the gate electrode of the pull-down transistor (24) of the other pair passes through a feedback transistor (30) which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals (WP1, WP2) can be impressed upon the gate electrode of the thus separated pull down transistor (24). Simultaneously, the signal on the first coupling point (16) can be selectively impressed upon any combination of a plurality of read lines (58, 60, 62). If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.

公开(公告)号：DE3480444D1

公开(公告)日：1989-12-14

申请号：DE3480444

申请日：1984-02-14

Applicant: IBM

Inventor： FURMAN ANATOL

IPC: G11C11/417 ,  G11C8/16 ,  G11C11/41 ,  G11C8/00

Abstract: © The present invention is especially directed towards a memory array (10) which utilizes means (24-26) for comparing the address inputs of word decoders (12-14) in the system such that, when a compare occurs, selected ones of the word decoders are disabled to prevent a multiple read and selected higher order read heads (22-23) are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder.

公开(公告)号：CA1043467A

公开(公告)日：1978-11-28

申请号：CA262156

申请日：1976-09-27

Applicant: IBM

Inventor： FURMAN ANATOL ,  KALTER HOWARD L ,  NAGEL JOHANN W

IPC: H01L27/10 ,  G11C11/24 ,  G11C11/35 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/07 ,  H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: SELF-ALIGNED INTEGRATED CIRCUITS Semiconductor integrated circuits, including, e. g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of a semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxidesilicon nitride, the dopant may be ion implanted through the insulating medium to form, e. g., the source and drain electrode of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e. g,, a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

公开(公告)号：DE3773715D1

公开(公告)日：1991-11-21

申请号：DE3773715

申请日：1987-02-24

Applicant: IBM

Inventor： FURMAN ANATOL

IPC: H03K3/03 ,  G06F1/04 ,  G06F1/06 ,  H03K5/15

公开(公告)号：DE3061954D1

公开(公告)日：1983-03-24

申请号：DE3061954

申请日：1980-02-21

Applicant: IBM

Inventor： FURMAN ANATOL

IPC: G11C11/41 ,  G11C11/416 ,  H03K5/02 ,  H03K5/08

公开(公告)号：FR2326038A1

公开(公告)日：1977-04-22

申请号：FR7626312

申请日：1976-08-25

Applicant: IBM

Inventor： FURMAN ANATOL ,  KALTER HOWARD L ,  NAGEL JOHANN W

IPC: H01L27/10 ,  G11C11/24 ,  G11C11/35 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/07 ,  H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  H01L27/06 ,  G11C11/34

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

公开(公告)号：DE3789726T2

公开(公告)日：1994-11-24

申请号：DE3789726

申请日：1987-02-17

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  FURMAN ANATOL

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/412 ,  G11C8/00

Abstract: A memory cell that allows simultaneous writing into the cell and reading from the cell includes a cross-coupled latch (10) in which two pairs of a load transistor (12, 14) and a pull-down transistor (20, 24) are connected at respective first and second coupling points (16, 18). However, the feedback path from the first coupling point (16) to the gate electrode of the pull-down transistor (24) of the other pair passes through a feedback transistor (30) which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals (WP1, WP2) can be impressed upon the gate electrode of the thus separated pull down transistor (24). Simultaneously, the signal on the first coupling point (16) can be selectively impressed upon any combination of a plurality of read lines (58, 60, 62). If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.