公开(公告)号：IE990422A1

公开(公告)日：2000-03-22

申请号：IE990422

申请日：1999-05-25

Applicant: IBM

Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  BEUKEMA BRUCE LEROY ,  FUHS RONALD EDWARD ,  KELLEY RICHARD ALLEN

IPC: G06F13/40 ,  G06F13/368

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.

公开(公告)号：DE69027416T2

公开(公告)日：1996-12-05

申请号：DE69027416

申请日：1990-11-13

Applicant: IBM

Inventor： BEUKEMA BRUCE LEROY

IPC: G06F13/00 ,  H04L12/42 ,  H04L12/40

Abstract: A redundant, fault-tolerant connection is provided from a local processing station (18) to a plurality of remote processing stations (20,22,24), each including an I/O bus and an associated I/O bus interface logic circuit (40,50,60). Two of the bus interface logic circuits (40,60) are connected directly to the processor interface circuit (30), via separate direct links (38,70). Intermediate bus interface circuits (50) and I/O busses of intermediate remote stations are connected between the two selected bus interface circuits, in a series arrangement including alternate link segments (46,48,56,58) and bus interface circuits(52,62). Each of the bus interface circuits has pass-through capability for transmitting data in either direction, and the links and link sections also are bidirectional, enabling transmission of data in either direction and on either path between the processor interface circuit and any of the remote stations, through any intervening stations. The processor interface circuit itself is intentionally configured without such pass-through capability.

公开(公告)号：DE69027416D1

公开(公告)日：1996-07-18

申请号：DE69027416

申请日：1990-11-13

Applicant: IBM

Inventor： BEUKEMA BRUCE LEROY

IPC: G06F13/00 ,  H04L12/42 ,  H04L12/40

Abstract: A redundant, fault-tolerant connection is provided from a local processing station (18) to a plurality of remote processing stations (20,22,24), each including an I/O bus and an associated I/O bus interface logic circuit (40,50,60). Two of the bus interface logic circuits (40,60) are connected directly to the processor interface circuit (30), via separate direct links (38,70). Intermediate bus interface circuits (50) and I/O busses of intermediate remote stations are connected between the two selected bus interface circuits, in a series arrangement including alternate link segments (46,48,56,58) and bus interface circuits(52,62). Each of the bus interface circuits has pass-through capability for transmitting data in either direction, and the links and link sections also are bidirectional, enabling transmission of data in either direction and on either path between the processor interface circuit and any of the remote stations, through any intervening stations. The processor interface circuit itself is intentionally configured without such pass-through capability.