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公开(公告)号：EP0801352A3
公开(公告)日：1998-10-14
申请号：EP97301904
申请日：1997-03-20
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVE MARK
CPC classification number: G06F13/36 , G06F13/4027
Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.
Abstract translation: 数据处理系统10包括处理器12，系统存储器15和多个外围设备401,403，以及一个或多个桥接器400，其可以连接处理器，存储器和外围设备以及其他主机或外围设备，诸如 网络。 诸如PCI主桥之类的桥连接在主总线（例如系统总线）14和次总线16之间。主桥400提供双主桥功能，其创建两个次级总线接口。 这允许在一个双主桥下增加加载能力，而在一个正常主桥下允许的插槽数量较少。 还包括用于提供仲裁控制和将交易转向相应总线接口的附加控制逻辑。 此外，还提供了跨两个辅助总线接口的对等支持。
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公开(公告)号：JPH11353267A
公开(公告)日：1999-12-24
申请号：JP11012299
申请日：1999-04-16
Applicant: IBM
Inventor： KELLEY RICHARD ALLEN , DANNY MARVIN NEIL , THURBER STEVEN MARK
Abstract: PROBLEM TO BE SOLVED: To provide an improved computer system having an extension bus which can add a peripheral device to the system. SOLUTION: In a method registering newly added peripheral device to a computer system 100, the peripheral device has a response by transmitting a state message to a bus of the system 100 within a prescribed period after the asserting of a reset signal supplied to the peripheral device is released and in response to the access trial given to the peripheral device. Thus, it's possible to evade the stoppage of a function and also to evade the necessity to reboot of the system 100 to initialize a new peripheral device to the system 100. If a a response is generated within an initialization waiting time period shorter than the prescribed period, the peripheral device is allowed to transmit a trial response in an early stage. Furthermore, the peripheral device can respond to a non-configuration cycle right after a configuration is completed. The internal logic of the peripheral device is initialized after responded by a state message.
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公开(公告)号：JPH11328098A
公开(公告)日：1999-11-30
申请号：JP6004299
申请日：1999-03-08
Applicant: IBM
Inventor： KELLEY RICHARD ALLEN , DANNY MARVIN NEIL , THURBER STEVE MARK
Abstract: PROBLEM TO BE SOLVED: To obtain a method and a system which support a multiple peripheral component interconnection (PCI) bus by a single PCI host bridge in a data processor. SOLUTION: In the method and system, a processor 48 and a system memory 50 are connected to a system bus 20. First and second PCI local busses are connected to the system bus through the PCI host bridge. First and second PCI local busses have plural inline electronic switches to divide the PCI local busses into PCI local bus segments which support plural PCI peripheral component slots. Plural pairs of inline electronic switches are opened and closed based on a bus control logic in the PCI host bridge 76 to provide a maximum of 14 PCI peripheral component slots, so as to access the system bus through the single PCI host bridge 76.
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公开(公告)号：JPH10177546A
公开(公告)日：1998-06-30
申请号：JP33156697
申请日：1997-12-02
Applicant: IBM
Inventor： LACKMAN ROBERT ANDREW , VANDERSLICE EDWARD ROBERT , KELLEY RICHARD ALLEN , INGERMAN DONALD , GENDUSO THOMAS BASILIO
IPC: G06F13/368
Abstract: PROBLEM TO BE SOLVED: To attain the almost optimum trade-off among all data types without adding any bus line by securing a part of scheduling intelligence at an arbiter with other parts secured at a device itself by means of a distributed scheduling method. SOLUTION: An arbiter 504 includes the independent arbitration class registers 506-1 to 506-n for (n) devices which can be connected to a bus 502. Each of these registers is corresponding to every specific device on the bus 502. A soft real-time device 508 includes a laxity threshold register 516, a clock 518 and a time-limit register 520. A loss-priority device 510 includes a buffer threshold register 522, a clock 524, a remainder buffer register 526 and a maximum elapsed time register 528. Then a hard real-time device 512 and a non-real- time device 514 immediately have the bus access requests when they have the transfer data, and accordingly no addition of registers is required.
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公开(公告)号：JPH1049482A
公开(公告)日：1998-02-20
申请号：JP8420597
申请日：1997-04-02
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVE MARK
Abstract: PROBLEM TO BE SOLVED: To efficiently process mixed transactions by connecting a 1st secondary bus and a 2nd secondary bus and connecting a bridge to a system bus which generates one logical bus supporting more peripheral devices than a previously set number. SOLUTION: A system 10 connects one host processor 12 to the 1st secondary bus 14 like a system bus that supports many peripheral devices which can be used by a multiprocessor system and also connects the other host processor 12 to the 1st secondary bus 14. Then the host bridge 20A is connected to the 1st secondary bus 14 and the 1st secondary bus 14 and 2nd secondary bus 16 are connected to each other. Further, a system memory 15 is connected to the 1st secondary bus 14 and 30 and 40 as other devices are connected to the 2nd secondary bus 16. Consequently, mixed transactions of the host bridge 20A can efficiently be processed.
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Patent Agency Ranking
公开(公告)号：DE69736872T2
公开(公告)日：2007-04-26
申请号：DE69736872
申请日：1997-03-20
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVE MARK
Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.
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公开(公告)号：DE69905689T2
公开(公告)日：2003-11-20
申请号：DE69905689
申请日：1999-11-19
Applicant: IBM
Inventor： NEAL DAN MARVIN , KELLEY RICHARD ALLEN
IPC: G06F13/40
Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.
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公开(公告)号：DE19953383A1
公开(公告)日：2000-06-21
申请号：DE19953383
申请日：1999-11-06
Applicant: IBM
Inventor： CLOUSER PAUL LEE , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN
Abstract: Two pairs of differential signal lines provided for each graphic port signal are routed close to each other on mother board selected from a group consisting of system chip set and graphic chip. The performance of the graphic port is enhanced, utilizing differential signaling between each of the signal line. - DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for the following: - (a) Accelerated graphic port performance enhancing apparatus; - (b) Enhanced accelerated graphic port
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公开(公告)号：DE19782087T1
公开(公告)日：1999-11-25
申请号：DE19782087
申请日：1997-09-30
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , NEAL DANNY MARVIN , KELLEY RICHARD ALLEN
IPC: G06F13/40
Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
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