公开(公告)号：CA867510A

公开(公告)日：1971-03-30

申请号：CA867510D

Applicant: IBM

Inventor： SELLERS FREDERICK F JR ,  BROWN DAVID T

公开(公告)号：CA1015067A

公开(公告)日：1977-08-02

申请号：CA182969

申请日：1973-10-09

Applicant: IBM

Inventor： BROWN DAVID T

IPC: G11C19/00 ,  G06F7/78 ,  G06F12/00 ,  G11C19/08

Abstract: 1398204 Digital data storage INTERNATIONAL BUSINESS MACHINES CORP 10 Sept 1973 [16 Nov 1972] 42404/73 Addition to 1313444 Heading G4C [Also in Division H3] The data storage system of the parent Specification 1,313,444, in which address bits a and data bits d of pages of data are stored in shift registers having recirculation loops L1 and L2 respectively including and excluding the read/ write access position K, is modified in that one bit (e.g. the lowest order) of a requested page address is used to control the direction of shifting so as to reduce the access time. Recently accessed pages are maintained in positions for successive shifting into the access position K in preference to other pages, the arrangement described storing pages with even-numbered addresses at the right-hand end of the registers and those with odd-numbered addresses at the left-hand end. The address of a requested page is supplied over lines 118, the lowest order address bit determining the direction of shift signals produced by a shift control unit until a comparator ACU detects a match, whereupon the shift control unit is conditioned for shifting in the opposite direction to restore the pages to the order of most recent access leaving the last accessed page in position K. The number of shifts required to access the desired page is counted in a reversible counter 200 which controls the number of shifts which take place in the restore operation in conjunction with a latch 310 which is set by the lowest order address bit. Magnetic bubble shift registers are described for use in the system, the shift control unit supplying a reversible rotating magnetic field to effect shifting in the registers. The use of FET registers is also mentioned.

公开(公告)号：CA945677A

公开(公告)日：1974-04-16

申请号：CA137076

申请日：1972-03-14

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  BROWN DAVID T ,  WALKER ERNEST L

IPC: G06F7/78 ,  G11C19/08

Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

公开(公告)号：CA762120A

公开(公告)日：1967-06-27

申请号：CA762120D

Applicant: IBM

Inventor： BROWN DAVID T

公开(公告)号：DE1172453B

公开(公告)日：1964-06-18

申请号：DEJ0020563

申请日：1961-09-21

Applicant: IBM

Inventor： ANDERSON ROBERT A ,  BROWN DAVID T

IPC: B60C3/00 ,  B60C11/00 ,  B60C11/01 ,  B60C11/04 ,  B60C11/11 ,  B60C15/02 ,  B60C17/04 ,  B60C19/00 ,  H03M5/00 ,  H03M7/12

Abstract: 979, 816. Address selection;coding. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 20,1961 [Sept. 21, 1960, No. 33717/61. Headings G4C and G4H. A five-digit binary coded (1-2-4-8) decimal number is used to represent one out of 1600 fourteen-bit combinations for the purpose e.g. of address selection. The 8-bit of the tens of thousands order is not used and the 1-, 2-, and 4-bit positions of a decimal register 10 are connected to orders 0 to 2 of a binary register 15, thus giving eight combinations. The 1-bit positions of the thousands, hundreds, and tens orders of the decimal register are connected to orders 3 to 5 of the binary register, also giving eight combinations. The or circuits 11 and 13 and and circuit 12 connected to the bit positions of the units order of the decimal register enter a one if the units decimal is five or more, a zero otherwise, into order 6 of the binary register, giving a further two combinations. In the tens, hundreds and thousands orders of the decimal register, each set of 2-, 4- and 8- bits can form five combinations, and a translator 20, comprising and and or circuits (Fig. 4 not shown), produces a binary representation in orders 7 to 13 of the binary register of that one of the 125 possible combinations formed by the nine inputs from the decimal register.