公开(公告)号：US3648255A

公开(公告)日：1972-03-07

申请号：US3648255D

申请日：1969-12-31

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  ORDEMANN FRED A JR ,  PRICER WILBUR D ,  VOGL NORBERT G JR

IPC: G11C19/00 ,  G11C19/18 ,  G06F7/34

CPC classification number: G11C19/188 ,  G11C19/00

Abstract: An electronic bulk storage having the characteristics of a sequential access storage device, such as a disk or a drum, but which has a low-access time and a variable instantaneous data rate. Data re stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feedback loop for recirculating data and when selected, a group of elements is read or written in parallel to a word at a time by electronically rotating the selected memory elements.

Abstract translation: 具有顺序访问存储装置（诸如盘或鼓）但具有低访问时间和可变瞬时数据速率的特征的电子批量存储器。 数据通过字被并行存储在由存储器选择矩阵选择的多个电子可旋转存储元件中。 每个元件具有用于再循环数据的反馈回路，并且当选择时，通过电子地旋转所选择的存储元件，一组元件一次读取或并行写入一个单词。

公开(公告)号：US3411143A

公开(公告)日：1968-11-12

申请号：US52041466

申请日：1966-01-13

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  ANDRIS PADEGS

IPC: G06F13/12 ,  G06F15/17

CPC classification number: G06F15/17 ,  G06F13/122 ,  G06F13/126

公开(公告)号：US3368207A

公开(公告)日：1968-02-06

申请号：US45505865

申请日：1965-05-12

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  CLARK WILLIAM A ,  HILL PETER R ,  SMITH RONALD M

IPC: G06F7/50 ,  G06F12/14 ,  G06F13/12

CPC classification number: G06F12/1441 ,  G06F7/50 ,  G06F13/122

公开(公告)号：US3872998A

公开(公告)日：1975-03-25

申请号：US36964773

申请日：1973-06-13

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  UBERBACHER EDWARD C

IPC: B65G1/04 ,  G06K17/00 ,  B65G1/06

CPC classification number: G06K17/0012 ,  B65G1/0435 ,  G06K17/00

Abstract: An improved tape storage rack and tape cartridge handler is provided for tape cartridges having a generally elongated cylindrical shape. The cartridge handler fetches the cartridge from any location in the rack but returns the cartridge to a position that is most readily accessible to the cartridge handler. Since the most recently fetched cartridges tend to be the most frequently used cartridges, this tape cartridge storage device tends to keep the most often used cartridges in the position for fastest access, and the average access time for the cartridge handler is reduced. In one embodiment of the invention cartridges are located in tandom on a removable sleeve in cells of the rack. A cartridge removed from a sleeve is returned to the outer most cartridge position of the sleeve so that the distance that the sleeve must be removed from its cell is kept low. In a second embodiment of the invention, cartridges are stacked one on top the other in vertical columns of the rack. When a cartridge is removed from a rack, any higher positioned cartridge is dropped one position and the cartridge that has been removed is later returned to the upper most position of its column in the rack. Thus, a high portion of the cartridge fetching operations are made at the uppermost positions of the rack.

Abstract translation: 提供了一种改进的磁带存储架和带盒处理器，用于具有大致细长的圆柱形形状的磁带盒。 墨盒处理器从机架中的任何位置取出墨盒，但将墨盒返回到墨盒处理器最容易接近的位置。 由于最近获取的盒式磁带往往是最常用的盒式磁带，所以这种磁带盒存储装置倾向于将最常用的盒式磁带保持在最快速存取的位置，并且减少了盒式处理器的平均访问时间。

公开(公告)号：US3670313A

公开(公告)日：1972-06-13

申请号：US3670313D

申请日：1971-03-22

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  BROWN DAVID T ,  WALKER ERNEST L

IPC: G06F7/78 ,  G11C19/08 ,  G11C11/14 ,  G11C19/00

CPC classification number: G06F7/78 ,  G11C19/0875

Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

Abstract translation: 本说明书公开了一种气泡域记忆，其中数据被安排用于根据其最后使用的即时性。 存储器包括多个并行移位寄存器，其中可并行访问数据。 换句话说，每个移位寄存器包含页或字的位，使得通过执行一个移位操作，可以访问页面或单词的所有位。 每个移位寄存器中的数据以其最后使用的顺序排列，使得具有K位位置的移位寄存器的访问位置K包含所使用的信息的最后位，移位寄存器中存取位置K之前的位置K-1包含 刚才使用的数据位在访问位置K中的数据等等。 在这些移位寄存器中，移位位置被布置成用于在移位寄存器的位置之间移位数据。 提供了两个这样的环路，其中一个环路包含所有移位位置，使得移位寄存器中任何位置的数据都可以移入寄存器的访问位置K进行读取或写入。 另一个环路包含移位寄存器的所有位置，但存在访问位置K.该第二循环用于在数据已经被移入访问位置K之后按照上次使用顺序重新排序移位寄存器中的数据，以便通过读取或写入 第一个循环。

公开(公告)号：US3588408A

公开(公告)日：1971-06-28

申请号：US3588408D

申请日：1969-06-26

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  UBERBACHER EDWARD C

IPC: H01H1/40 ,  H01H29/00

CPC classification number: H01H1/403 ,  H01H29/00

Abstract: A PRINTED CIRCUIT ON A CIRCUIT BOARD IS ARRANGED TO GIVE A SEQUENTIAL PULSE OUTPUT WHEN THE CIRCUIT IS COMPLETED. A CHANNEL IS ATTACHED TO THE CIRCUIT BOARD SO AS TO CROSS VARIOUS CIRCUIT LINES. AT EACH CROSS POINT BETWEEN A CIRCUIT LINE AND THE CHANNEL, THERE IS A GAP IN THE CIRCUIT SUCH THAT THE GAP CAN BE BRIDGED BY A CONDUCTIVE PELLET TRAVELLING THROUGH THE CHANNEL THUS COMPLETING THE CIRCUIT TO PROVIDE THE PULSE OUTPUT. THE DEVICE CAN BE PROGRAMMED OR PRECONDITIONED BY PROVIDING A SECOND CHANNEL WHICH CROSSES THE CIRCUIT LINES AND WHICH HAS GAPS IN THE CIRCUIT LINES WHERE THE SECOND CHANNEL CROSSES. A RESERVOIR OF CONDUCTIVE MATERIAL IS CONNECTED TO THE SECOND CHANNEL AND IS ADAPTED TO BE ENERGIZED IN ACCORDANCE WITH AN ASSOCIATED DEVICE SUCH AS A CAMMED COUNTER WHEEL. THE CONDUCTIVE MATERIAL RISES AND EBBS IN THE SECOND CHANNEL IN ACCORDANCE WITH PRESSURE APPLIED TO THE RESERVOIR THUS BRIDGING A CORRESPONDING NUMBER OF GAPS. THE CONDUCTIVE PELLET, AS IT PASSES THROUGH THE FIRST CHANNEL, PRODUCES PULSES AT THE OUTPUT BY COMPLETING THE CIRCUITS OF ONLY THOSE CIRCUIT LINES WHICH ARE PRECONDITIONED BY HAVING THE SECOND GAPS IN THE SECOND CHANNEL BRIDGED BY THE CONDUCTIVE MATERIAL THEREIN.

公开(公告)号：US3581286A

公开(公告)日：1971-05-25

申请号：US3581286D

申请日：1969-01-13

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G06F13/10 ,  G06F13/40 ,  G06F15/16

CPC classification number: G06F13/4022

Abstract: An input/output interface switching apparatus for switching I/O interfaces connecting I/O control units between channels. The I/O interface switching apparatus provides means for attaching one or more strings of control units to one or more channels and provides a means for switching these strings of control units between the channels under configuration control. The switching apparatus is so arranged that a single failure within one interface affects at most only the channel to which the interface is associated. A switching matrix is provided, within the apparatus, which is physically centralized to minimize the number of I/O interface cables and connectors. The switching functions are, however, logically decentralized from a reliability standpoint so that a single component failure will not result in total switching system failure.

公开(公告)号：US3697962A

公开(公告)日：1972-10-10

申请号：US3697962D

申请日：1970-11-27

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  JEN TEH-SEN ,  PRICER W DAVID

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40

CPC classification number: H01L27/1023 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/075 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: This specification discloses a stored charged storage cell for implementation in monolithic memories. The storage cells are fabricated in an array form and are connected to accessing means for reading and writing information into and out of the array. An integrated circuit diffused common sensing line is connected to either selected rows or columns for reading and writing. These sensing lines are connected to a switchable current source. The cell itself clamps the output voltage swing and thus reduces power dissipation. The storage cells each comprise a pair of semiconductor elements for storing digital information on an associated parasitic capacitor. The pair of semiconductor devices are interconnected and operated in an AC mode so as to eliminate direct current paths and thus further prevent unnecessary power dissipation.

Abstract translation: 本说明书公开了一种用于在单片存储器中实现的存储的充电存储单元。 存储单元以阵列形式制造并连接到用于将信息读入和写入阵列的访问装置。 集成电路漫射的公共感测线路连接到所选择的行或列用于读取和写入。 这些感测线路连接到可切换的电流源。 电池本身夹紧输出电压摆幅，从而降低功耗。 存储单元各自包括一对半导体元件，用于在关联的寄生电容器上存储数字信息。 该对半导体器件以AC模式互连和操作，以消除直流电流路径，从而进一步防止不必要的功率耗散。

公开(公告)号：US3654622A

公开(公告)日：1972-04-04

申请号：US3654622D

申请日：1969-12-31

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G11C19/00 ,  G11C19/18 ,  G06F7/34

CPC classification number: G11C19/188 ,  G11C19/00

Abstract: An electronic bulk storage having the characteristics of a sequential access storage device. Data are stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feedback loop for recirculating data and when selected, a group of elements at an address N is read in parallel a word at a time by electronically rotating data bits stored in the selected memory elements at an address. Controls are provided to select memory elements N+1 whenever elements at address N are selected by the selection matrix. First data is read out of the elements at address N and then data is read out of the elements at address N+1 without any time lost for reselection of memory elements.

Abstract translation: 具有顺序存取存储装置特征的电子批量存储装置。 数据以字为单位存储在由存储器选择矩阵选择的多个电子可旋转存储元件中。 每个元件具有用于再循环数据的反馈回路，并且当选择时，通过以存储在所选择的存储器元件中的地址的数字位电子地旋转，一个字地并行读取地址N处的一组元件。 当选择矩阵选择地址N的元素时，提供控制来选择存储元件N + 1。 从地址N的元素中读出第一数据，然后从地址N + 1的元素中读出数据，而无需任何时间丢失用于重新选择存储器元件。

公开(公告)号：US3601807A

公开(公告)日：1971-08-24

申请号：US3601807D

申请日：1969-01-13

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  PRICER WILBUR D

IPC: G06F13/40 ,  H04Q5/14 ,  H04M3/22

CPC classification number: G06F13/4022

Abstract: An input/output interface switching apparatus for switching I/O interfaces connecting I/O control units between channels. A matrix of transistor cross-point switches is provided for attaching one or more strings of control units to one or more channels. These strings of control unit are switched between the channels under configuration control. The cross-points are arranged so that a single failure within one interface affects at most only the channel to which the interface is associated. The switching matrix is physically centralized to minimize the number of I/O interface cables and connectors. The switching functions are, however, logically decentralized from a reliability standpoint so that a single component failure does not result in total switching system failure.