DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION

    公开(公告)号:SG193162A1

    公开(公告)日:2013-09-30

    申请号:SG2013057922

    申请日:2010-11-08

    Applicant: IBM

    Abstract: 23 DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION AbstractA system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The10 preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional15 processing. Fig. 1

    DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION

    公开(公告)号:CA2800643A1

    公开(公告)日:2011-12-01

    申请号:CA2800643

    申请日:2010-11-08

    Applicant: IBM

    Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.

    13.
    发明专利
    未知

    公开(公告)号:DE60131247D1

    公开(公告)日:2007-12-20

    申请号:DE60131247

    申请日:2001-09-24

    Applicant: IBM

    Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of > 99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

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