公开(公告)号：DK3532921T3

公开(公告)日：2021-03-29

申请号：DK17791010

申请日：2017-10-17

Applicant: IBM

Inventor： BRADBURY JONATHAN ,  SCHWARZ ERIC ,  MUELLER SILVIA MELITTA ,  GSCHWIND MICHAEL KARL ,  OLSSON BRETT

IPC: G06F9/30 ,  G06F9/455

公开(公告)号：AU2017336196B2

公开(公告)日：2020-07-09

申请号：AU2017336196

申请日：2017-09-26

Applicant: IBM

Inventor： BRADBURY JONATHAN ,  COPELAND REID ,  MUELLER SILVIA MELITTA

IPC: G06F9/30

Abstract: An instruction generates a value for use in processing within a computing environment. The instruction obtains a sign control associated with the instruction, and shifts an input value of the instruction in a specified direction by a selected amount to provide a result. The result is placed in a first designated location in a register, and the sign, which is based on the sign control, is placed in a second designated location of the register. The result and the sign provide a signed value to be used in processing within the computing environment.

公开(公告)号：GB2528443A

公开(公告)日：2016-01-27

申请号：GB201412875

申请日：2014-07-21

Applicant: IBM

Inventor： LICHTENAU CEDRIC ,  MUELLER SILVIA MELITTA ,  CARLOUGH STEVEN R

IPC: G06F7/57 ,  G06F11/07

Abstract: Checking a correctness of computations of an arithmetic logic unit circuit 10, the arithmetic logic unit circuit 10 providing a computation result as a first number 12. The method comprises providing the computation result increased by a constant 16 by the arithmetic logic unit circuit 10 as a second number 14 and comparing a sum of the first number 12 and the constant 16 to the second number 14 then reporting an error 20 if the comparing operation does not indicate an equal result. Alternatively the first number may be summed with the negated second number 14 and the constant 16 and an error reported if the summing operation does not result to minus 1. The computation result and the computation result being increased by a constant may be calculated in parallel. The method allows the reuse of computed results to check for correctness of computations.

公开(公告)号：GB2506871A

公开(公告)日：2014-04-16

申请号：GB201218112

申请日：2012-10-10

Applicant: IBM

Inventor： LAYER CHRISTOPHE ,  MUELLER SILVIA MELITTA ,  KROENER MICHAEL ,  SCHELM KERSTIN

IPC: G06F7/544 ,  G06F7/49

Abstract: An arithmetic operation, such as an SRT computation of a division, square root, addition, subtraction or multiplication, in a data processing unit (216), preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently, at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step. A multiplexing unit may select the final result. Iteration may use accumulating digit values concatenated to previous results using a radix.

公开(公告)号：ZA201902290B

公开(公告)日：2019-11-27

申请号：ZA201902290

申请日：2019-04-11

Applicant: IBM

Inventor： MUELLER SILVIA MELITTA ,  COPELAND REID ,  BRADBURY JONATHAN ,  CARLOUGH STEVEN

Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.

公开(公告)号：DE112018000140T5

公开(公告)日：2019-07-11

申请号：DE112018000140

申请日：2018-01-08

Applicant: IBM

Inventor： KROENER MICHAEL KLAUS ,  KRAUTZ UDO ,  BABINSKY TINA ,  MUELLER SILVIA MELITTA ,  WAGNER ANDREAS

IPC: G06F7/483

Abstract: Gleitkommaeinheit (10), die so konfiguriert ist, dass sie eine verschmolzene Multiplikations-Additions-Operation auf drei 128 Bit breiten Operanden (100, 102, 104) durchführt, wobei die Einheit aufweist: (i) einen 113x113-Bit-Multiplikator (14); (ii) einen Linksverschieber (18); (iii) einen Rechtsverschieber (20); (iv) eine Auswahlschaltung (24), die einen 3-zu-2-Komprimierer (25) aufweist; (v) einen Addierer (26), der mit dem Datenfluss von der Auswahlschaltung (24) verbunden ist; (vi) einen ersten Rückmeldepfad (36), der einen Übertragausgang (91) des Addierers (26) mit der Auswahlschaltung (24) verbindet; und (vii) einen zweiten Rückmeldepfad (38), der den Ausgang des Addierers (26) mit den Verschiebern (18, 20) verbindet, um ein breites Zwischenergebnis (86) über die Verschieber (18, 20) weiterzuleiten.

公开(公告)号：AU2017333768A1

公开(公告)日：2019-04-04

申请号：AU2017333768

申请日：2017-09-21

Applicant: IBM

Inventor： BRADBURY JONATHAN ,  COPELAND REID ,  MUELLER SILVIA MELITTA ,  SCHWARZ ERIC ,  CARLOUGH STEVEN

IPC: G06F7/491

Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

公开(公告)号：CA3036123A1

公开(公告)日：2018-04-05

申请号：CA3036123

申请日：2017-09-21

Applicant: IBM

Inventor： MUELLER SILVIA MELITTA ,  COPELAND REID ,  BRADBURY JONATHAN ,  CARLOUGH STEVEN

IPC: G06F7/491

Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.

公开(公告)号：BRPI1102360A2

公开(公告)日：2015-07-28

申请号：BRPI1102360

申请日：2011-05-30

Applicant: IBM

Inventor： COWLISHAW MICHAEL F ,  MUELLER SILVIA MELITTA ,  SCHWARZ ERIC ,  YEH PHIL C

IPC: G06F7/491 ,  G06F7/499

Abstract: Detecção de exceção de qumitum de ponto flutuante decimal método compreendendo as seguintes etapas: desempenhar as seguintes funções com um processador: aceitar pelo menos um operando com ponto flutuante decimal; executar uma operação de ponto flutuante decimal sobre pelo menos um ponto flutuante decimal operando para produzir um resultado de ponto flutuante decimal; determinar, em resposta à execução, que o resultado de ponto flutuante decimal não consegue manter um quantum preferido, o quantum preferido indicando um valor definido representado por um dígito menos significativo, de um significando do resultado ponto flutuante decimal, e fornecer, em resposta à determinação de que o resultado do ponto flutuante decimal não consegue manter o quantum preferido, uma saida indicando uma exceção quântica, a exceção quántica que ocorre em resposta ao resultado do ponto flutuante decimal não manter o quantum preferido.

公开(公告)号：AU2010353843B2

公开(公告)日：2014-08-28

申请号：AU2010353843

申请日：2010-11-08

Applicant: IBM

Inventor： SCHWARZ ERIC MARK ,  YEH PHIL ,  COWLISHAW MICHAEL FREDERIC ,  MUELLER SILVIA MELITTA

IPC: G06F9/302 ,  G06F7/491 ,  G06F7/499 ,  G06F9/38

Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.