公开(公告)号：SG146549A1

公开(公告)日：2008-10-30

申请号：SG2008019333

申请日：2008-03-10

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHAN VICTOR W C ,  SUNFEI FANG ,  DYER THOMAS W ,  LI JINGHONG H ,  JIANG YAN ,  UTOMO HENRY K ,  JUNG TANG TECK

Abstract: SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET Methods of forming a silicide in an embedded silicon germanium (eSiGe) source/drain region using a silicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen- containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.

公开(公告)号：SG142220A1

公开(公告)日：2008-05-28

申请号：SG2007065840

申请日：2007-09-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES NOTH AME

Inventor： MENG LEE YONG ,  DYER THOMAS W ,  SUNFEI FANG ,  JIANG YAN ,  SIDDHARTHA PANDA

Abstract: POST-SILICIDE SPACER REMOVAL A method forms a gate conductor over a substrate, spacers on sidewalls of the gate conductor and impurity regions in regions of the substrate not protected by the gate conductor and spacers. The impurity regions are silicided. A conformal protective layer followed by a non-conformal sacrificial layer (e.g., that can be selectively removed with respect to the protective layer) are formed over the silicided regions, spacers and gate conductor. An etching process removes the relatively thinner regions of the sacrificial layer overlying the spacers while retaining the relatively thicker regions of the sacrificial layer overlying the substrate. This allows the removal of the protective layer portions that cover the spacers while retaining the portions that cover the silicide. With the spacers now exposed and the silicide protected by the protective and sacrificial layers, it becomes possible to safely remove the spacers without affecting the silicide.

公开(公告)号：DE102004060891A1

公开(公告)日：2005-08-11

申请号：DE102004060891

申请日：2004-12-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： RADENS CARL ,  DYER THOMAS W ,  SUNG CHUN-YUNG ,  DIVAKARUNI RAMACHANDRA ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：SG152165A1

公开(公告)日：2009-05-29

申请号：SG2008075814

申请日：2008-10-10

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  INFINEON TECHNOLOGIES AG ,  IBM

Inventor： JUNG KIM JUN ,  SUNG KWON O ,  HO LEE MIN ,  JINE PARK SANG ,  DYER THOMAS W ,  SUNFEI FANG ,  WIDODO JOHNNY

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode. Figure 10

公开(公告)号：SG142221A1

公开(公告)日：2008-05-28

申请号：SG2007065857

申请日：2007-09-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： MENG LEE YONG ,  DYER THOMAS W ,  SUNFEI FANG ,  JA-HUM KU

Abstract: SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer. Fig. 27