公开(公告)号：WO03005447A8

公开(公告)日：2004-02-19

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：WO03005447A2

公开(公告)日：2003-01-16

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。 该工艺消除了对M0金属化层的需求。

公开(公告)号：DE10334946B4

公开(公告)日：2006-03-09

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：DE10307822B4

公开(公告)日：2005-08-18

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：DE10307822A1

公开(公告)日：2003-11-06

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：DE10334946A1

公开(公告)日：2004-03-18

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：DE102004060891A1

公开(公告)日：2005-08-11

申请号：DE102004060891

申请日：2004-12-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： RADENS CARL ,  DYER THOMAS W ,  SUNG CHUN-YUNG ,  DIVAKARUNI RAMACHANDRA ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：DE10324491B4

公开(公告)日：2005-07-14

申请号：DE10324491

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MALIK RAIEEV ,  RENGARAJAN RAIESH

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.