公开(公告)号：CA2299348A1

公开(公告)日：1999-04-29

申请号：CA2299348

申请日：1998-10-14

Applicant: IBM

Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：GB2324392A

公开(公告)日：1998-10-21

申请号：GB9803618

申请日：1998-02-23

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS ,  HILLIER III PHILIP ROGERS

IPC: G06F9/38 ,  G06F9/46

Abstract: Instructions for an active thread, currently being processed by a multithread processor, are stored in a primary instruction queue 10, and instructions for a dormant thread, not currently being executed, are stored in a thread switch instruction queue 14. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch queue are transferred to the primary instruction queue. Use of the additional, thread switch instruction queue eliminates the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread.