公开(公告)号：JP2007257637A

公开(公告)日：2007-10-04

申请号：JP2007071882

申请日：2007-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WOTTRENG ANDREW HENRY ,  CLARK SCOTT DOUGLAS

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F2212/1016

Abstract: PROBLEM TO BE SOLVED: To reduce the consumption of internode bandwidth by communications maintaining coherence between accelerators and CPUs. SOLUTION: The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过维护加速器和CPU之间的一致性来减少节间带宽的消耗。 解决方案：CPU和加速器可能会聚集在多处理环境中的单独节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2012181860A

公开(公告)日：2012-09-20

申请号：JP2012106285

申请日：2012-05-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WOTTRENG ANDREW HENRY ,  CLARK SCOTT DOUGLAS

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F2212/1016

Abstract: PROBLEM TO BE SOLVED: To reduce consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs.SOLUTION: CPUs 210 and accelerators 220 may be clustered on separate nodes in a multiprocessing environment. Each node 0, 1 that contains a shared memory device 212, 222 may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, command and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, inter-chip bandwidth consumed for maintaining coherence may be reduced.

Abstract translation: 要解决的问题：通过维护加速器和CPU之间的一致性来减少节点间带宽的消耗。 解决方案：CPU 210和加速器220可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备212,222的每个节点0,1可以维护目录以跟踪可能已经在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点之外时，命令和地址才可以发送到其他节点处的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JPH10275100A

公开(公告)日：1998-10-13

申请号：JP4919098

申请日：1998-03-02

Applicant: IBM

Inventor： LARSEN TROY DALE ,  RANDOLPH JACK CHRIS ,  WOTTRENG ANDREW HENRY

IPC: G06F11/34

Abstract: PROBLEM TO BE SOLVED: To monitor the performance for every thread in a multi-thread processor by recording individually the 1st and 2nd events which are generated in response to the 1st and 2nd threads respectively. SOLUTION: A processor 10 includes a performance monitor 50 which supports-the performance monitoring jobs independent of each of plural parallel threads which are supported by the processor 10 itself. The monitor 50 receives the event occurrences which are generated by the operations of an IU 25, an FP 26, an FX 30, an SC 23, a BIU 12 and an L2 cache interface 58 as its input. Then the selected one of these many event occurrences is recorded into a software readable/writable PMC(performance monitor counter) that is included in the monitor 50.

公开(公告)号：CA2299348C

公开(公告)日：2004-10-19

申请号：CA2299348

申请日：1998-10-14

Applicant: IBM

Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  FLYNN WILLIAM THOMAS ,  EICKEMEYER RICHARD JAMES

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instractions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：GB2324393B

公开(公告)日：2002-03-13

申请号：GB9803673

申请日：1998-02-24

Applicant: IBM

Inventor： LARSEN TROY DALE ,  RANDOLPH JACK CHRIS ,  WOTTRENG ANDREW HENRY

IPC: G06F11/34

Abstract: A method and system for performance monitoring within a multithreaded processor are provided. The system includes a processor responsive to instructions within first and second threads and a performance monitor that separately records a first event generated by the processor in response to the first thread and a second event generated by the processor in response to the second thread. In one embodiment, the processor has first and second modes of operation. In this embodiment, when the performance monitor is operating in the first mode, a first counter within the performance monitor increments in response to each occurrence of the first event and a second counter within the performance monitor increments in response to each occurrence of the second event. Alternatively, when the performance monitor is operating in the second mode, the first counter increments in response to each occurrence of the first event and in response to each occurrence of the second event.

公开(公告)号：CA2299348A1

公开(公告)日：1999-04-29

申请号：CA2299348

申请日：1998-10-14

Applicant: IBM

Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：DE69029995D1

公开(公告)日：1997-04-03

申请号：DE69029995

申请日：1990-10-09

Applicant: IBM

Inventor： LEMAIRE CHARLES ARTHUR ,  WOTTRENG ANDREW HENRY

IPC: G06F9/30 ,  G06F9/46 ,  G06F15/16 ,  G06F15/177

Abstract: A computer system in which each of certain critical instructions, all performing multiple main storage accesses to shared data, have the appearance of executing required main storage accesses atomically with respect to a predefined set or class of instructions. The instructions in each set, referred to as relatively atomic instructions, are grouped together based on the data structure or object class they affect. The computer system comprises (a) shared memory means (203); (b) a plurality of processors (201, 202,..., n) coupled to said shared memory means, wherein each processor has an instruction set divided into a plurality of instruction classes; (c) means for constraining an instruction in one of said classes running on one of said plurality of processors, to run atomically relative to any instruction in said class running on any other of said plurality of processors in said system; (d) means for signalling (280, 281, 282) between said processors to indicate when an instruction in one of said classes is running and for providing an indication of which particular class the instruction is a member of; and (e) means for selectively delaying the operation of all other instructions in said particular class on every other processor in said system.

公开(公告)号：CZ20001437A3

公开(公告)日：2000-07-12

申请号：CZ20001437

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  LEVENSTEIN SHELDON BERNARD ,  WOTTRENG ANDREW HENRY

IPC: G06F9/38 ,  G06F9/46

公开(公告)号：HK1015049A1

公开(公告)日：1999-10-08

申请号：HK99100012

申请日：1999-01-05

Applicant: IBM

Inventor： LARSEN TROY DALE ,  RANDOLPH JACK CHRIS ,  WOTTRENG ANDREW HENRY

IPC: G06F11/34 ,  G06F

Abstract: A method and system for performance monitoring within a multithreaded processor are provided. The system includes a processor responsive to instructions within first and second threads and a performance monitor that separately records a first event generated by the processor in response to the first thread and a second event generated by the processor in response to the second thread. In one embodiment, the processor has first and second modes of operation. In this embodiment, when the performance monitor is operating in the first mode, a first counter within the performance monitor increments in response to each occurrence of the first event and a second counter within the performance monitor increments in response to each occurrence of the second event. Alternatively, when the performance monitor is operating in the second mode, the first counter increments in response to each occurrence of the first event and in response to each occurrence of the second event.

公开(公告)号：SG60202A1

公开(公告)日：1999-02-22

申请号：SG1998000357

申请日：1998-02-19

Applicant: IBM

Inventor： LARSEN TROY DALE ,  RANDOLPH JACK CHRIS ,  WOTTRENG ANDREW HENRY

IPC: G06F11/34 ,  G06F11/30

Abstract: A method and system for performance monitoring within a multithreaded processor are provided. The system includes a processor responsive to instructions within first and second threads and a performance monitor that separately records a first event generated by the processor in response to the first thread and a second event generated by the processor in response to the second thread. In one embodiment, the processor has first and second modes of operation. In this embodiment, when the performance monitor is operating in the first mode, a first counter within the performance monitor increments in response to each occurrence of the first event and a second counter within the performance monitor increments in response to each occurrence of the second event. Alternatively, when the performance monitor is operating in the second mode, the first counter increments in response to each occurrence of the first event and in response to each occurrence of the second event.