公开(公告)号：JPH05134923A

公开(公告)日：1993-06-01

申请号：JP29040891

申请日：1991-10-11

Applicant: IBM

Inventor： FUJITA NORIO ,  AIDA MITSUHIRO

IPC: G06F12/06

Abstract: PURPOSE: To attain interleave access in an always optimal state by detecting which memory unit an address area belongs to, and detecting whether or not each detected memory unit belongs to a bank enabling interleave. CONSTITUTION: A controlling means 46 of a memory controller 18 detects whether or not memory units specified by first and second memory unit specifying means 44A and 44B belong to different banks. Moreover, when the presence of the memory units in the different banks is detected, a physical address signal is generated in a configuration for performing interleave access to both banks 28A and 28B, and when the presence of the memory units in the same bank is detected, a physical address for performing non-interleave access to one of the both banks is generated. In the configuration for performing the interleave access, two of 16 RAS signal lines individually provided at each of the total 16 memory units are simultaneously made active through the both banks.

公开(公告)号：BR9203840A

公开(公告)日：1993-05-04

申请号：BR9203840

申请日：1992-10-01

Applicant: IBM

Inventor： FUJITA NORIO ,  GOHDA MITSUHIRO

IPC: G06F12/06 ,  G06F12/00

Abstract: A memory controller 18 of a data processing system controls access to a memory having a plurality of memory banks of memory units. The banks operate in either an interleave or non-interleave access operation. The controller has map forming means 42A and 42B to map the memory units arranged in first and second predetermined orders, the second map beng in reverse order relative to the first map. Memory unit selection means 44A and 44B select which of the memory units in each of the maps an address from a cpu or a DMA controller is assigned to and control means 46 generates the physical location address in interleave or non-interleave operation in accordance with the selected unit being assigned to different banks or the same bank.

公开(公告)号：CA2079353A1

公开(公告)日：1993-04-12

申请号：CA2079353

申请日：1992-09-24

Applicant: IBM

Inventor： FUJITA NORIO ,  GOHDA MITSUHIRO

IPC: G06F12/06 ,  G06F12/10 ,  G06F13/16

Abstract: JA9-91-027 MEMORY CONTROLLER AND DATA PROCESSING SYSTEM In the case where memory units are allocated to a plurality of interleavable banks, to provide a function for forming a plurality of memory maps which is comprised of the memory units in all banks arranged in predetermined different orders according to the number of said banks, detecting that an address area within a predetermined range involving a CPU address or addresses belongs to which of the memory units on each of a plurality of said memory maps, and determining whether each of detected memory units belongs to interleavable banks each other.