公开(公告)号：JPH06250937A

公开(公告)日：1994-09-09

申请号：JP2110593

申请日：1993-02-09

Applicant: IBM

Inventor： FUJITA NORIO ,  FUJITA NOBUHITO ,  YAMAZAKI SATORU ,  AIDA MITSUHIRO

IPC: G06F11/10 ,  G06F12/16

Abstract: PURPOSE: To suppress the increase of the number of times of memory access at the time of adding an ECC code to each data with specific length and operating an ECC processing, and to prevent the executing speed of a program from being sharply deteriorated even at the time of executing the ECC processing. CONSTITUTION: At the time of adding an ECC code to each data with specific bit length and writing the data in a memory element 20, when the length of writing data from a CPU 10 is less than the specific bit length, data previously read from the memory element 20 are held in a mean 42 different from the memory element 20, and data with the specific bit length are generated based on the held data and the writing data from the CPU 10. Thus, the ECC processing can be attained even when the reading from the memory is not necessarily operated before the writing in the memory.

公开(公告)号：JPH05127994A

公开(公告)日：1993-05-25

申请号：JP29040791

申请日：1991-10-11

Applicant: IBM

Inventor： FUKUSHIMA TOSHIAKI ,  AIDA MITSUHIRO ,  YAMAZAKI SATORU

IPC: G06F12/08 ,  G06F12/16

Abstract: PURPOSE: To quickly attain the test of a system memory by fetching a code part in a test program in a cache memory, and by not fetching a data part in the cache memory. CONSTITUTION: A cache memory 40 and a stage signal generating means 42 are incorporated in a microprocessor (CPU) 10. The cache memory 40 is enabled or disabled by a cache control signal inputted to the CPU 10. The sate signal generating means 42 generates a data/code signal (+D/-C signal) indicating whether the CPU 10 performs access to the code part of a program stored in a system memory 30 or performs access to the data part. When the +D/-D signal is a high level, the CPU 10 performs access to the data part, and when the +D/-D signal is a low level, the CPU 10 performs access to the code part.

公开(公告)号：JPH05134923A

公开(公告)日：1993-06-01

申请号：JP29040891

申请日：1991-10-11

Applicant: IBM

Inventor： FUJITA NORIO ,  AIDA MITSUHIRO

IPC: G06F12/06

Abstract: PURPOSE: To attain interleave access in an always optimal state by detecting which memory unit an address area belongs to, and detecting whether or not each detected memory unit belongs to a bank enabling interleave. CONSTITUTION: A controlling means 46 of a memory controller 18 detects whether or not memory units specified by first and second memory unit specifying means 44A and 44B belong to different banks. Moreover, when the presence of the memory units in the different banks is detected, a physical address signal is generated in a configuration for performing interleave access to both banks 28A and 28B, and when the presence of the memory units in the same bank is detected, a physical address for performing non-interleave access to one of the both banks is generated. In the configuration for performing the interleave access, two of 16 RAS signal lines individually provided at each of the total 16 memory units are simultaneously made active through the both banks.