公开(公告)号：DE1170177B

公开(公告)日：1964-05-14

申请号：DEJ0020997

申请日：1961-11-30

Applicant: IBM

Inventor： GINDI ABRAHAM M

IPC: B41J9/26 ,  H03K3/26

公开(公告)号：CH616791A5

公开(公告)日：1980-04-15

申请号：CH804777

申请日：1977-06-30

Applicant: IBM

Inventor： GINDI ABRAHAM M

IPC: G06F13/00 ,  H04L1/00 ,  H04L12/42 ,  H04L25/49 ,  H04L7/04 ,  H04L5/22

Abstract: A method and apparatus for synchronizing frame delimited bit stream messages on a high speed loop for communication among storage system elements. The method especially minimizes the time for attaining frame and byte synchronization among terminals attaching storage elements to the loop. The method comprises the steps of (1) synchronizing terminals downstream from a faulty terminal to a first synch reference as generated by the faulty terminal and further (2) synching the terminals upstream therefrom to a second synch pattern generated by the primary terminal responsive to the first reference. As a consequence, the system resynchs as a function of resynching of the faulty station alone. Transmission efficiency is improved by logically assigning for loop attachment only those loop secondary terminals whose storage elements have an aggregate bandwidth less than the available instantaneous loop bandwidth. Further improvement is obtained by dynamically varying the frame assignments. Finally, efficiency is achieved by minimizing the time to acquire and reacquire byte and frame synchrony loss caused when the loop is initially powered on or by transient electrical disturbances.

公开(公告)号：CA1032674A

公开(公告)日：1978-06-06

申请号：CA214165

申请日：1974-11-19

Applicant: IBM

Inventor： GINDI ABRAHAM M ,  LANG DONALD J

IPC: G06F13/38 ,  G06F9/46 ,  G06F13/00 ,  G06F13/362

公开(公告)号：DE2728010A1

公开(公告)日：1978-02-16

申请号：DE2728010

申请日：1977-06-22

Applicant: IBM

Inventor： GINDI ABRAHAM M

IPC: G06F13/00 ,  H04L1/00 ,  H04L12/42 ,  H04L25/49 ,  G11B5/86 ,  G11D1/00 ,  G06F3/00

Abstract: A method and apparatus for synchronizing frame delimited bit stream messages on a high speed loop for communication among storage system elements. The method especially minimizes the time for attaining frame and byte synchronization among terminals attaching storage elements to the loop. The method comprises the steps of (1) synchronizing terminals downstream from a faulty terminal to a first synch reference as generated by the faulty terminal and further (2) synching the terminals upstream therefrom to a second synch pattern generated by the primary terminal responsive to the first reference. As a consequence, the system resynchs as a function of resynching of the faulty station alone. Transmission efficiency is improved by logically assigning for loop attachment only those loop secondary terminals whose storage elements have an aggregate bandwidth less than the available instantaneous loop bandwidth. Further improvement is obtained by dynamically varying the frame assignments. Finally, efficiency is achieved by minimizing the time to acquire and reacquire byte and frame synchrony loss caused when the loop is initially powered on or by transient electrical disturbances.

公开(公告)号：DE2728246A1

公开(公告)日：1978-02-02

申请号：DE2728246

申请日：1977-06-23

Applicant: IBM

Inventor： GINDI ABRAHAM M ,  LANG DONALD JOHN

IPC: G06F13/00 ,  H04L7/08 ,  H04L12/42 ,  G06F3/00 ,  G11B5/86 ,  G11D1/00 ,  H04L25/02

Abstract: 1530757 Loop systems INTERNATIONAL BUSINESS MACHINES CORP 20 June 1977 [26 July 1976] 25729/77 Heading H4P A unidirectional loop system for passage of data between central processing unit CPU, Fig. 1, and {disc or tape} storage devices 3, information being organized into frames, the loop delay greatly exceeding frame duration in view of the high data rate, is characterized by the algorithms, Figs. 4, 5 determining the inter-relation between particular types of received frame, and the corresponding despatched frame for the loop controller 7, or primary terminal, and the device adaptors, or secondary terminals. In particular, Fig. 4, if the loop controller receives a write request frame from a particular adapter, it responds by replacing that frame with a data filled frame addressed to that adapter, or if it receives a frame full of data from an adapter, it stores that data and replaces the frame with an empty, unassigned one. Each frame comprises bit, and frame synchronizing bits, address bits, and a numer of 8-bit bytes, available for transmission of data, commands, or status in response to such commands; together with further bits, corresponding to a cyclical redundancy code and parity bits for error checking. Further frames are devoted to the establishment or checking of frame and bit sync. Fig. 4 shows the nature of processing and replacement for the loop controller, that for each adapter being disclosed in Fig. 5. Figs. 2 and 3 (not shown) disclose the nature of the data handling, in the loop controller 7 and adapter 19, and that in the serial converters 13, 15, 17 ... respectively. The loop passes information in bipolar differential code, Fig. 8 (not shown) using a pair of parallel paths.