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    Parallel multiplexed loop interface for data transfer and control between data processing systems and subsystems
    5.
    发明授权
    Parallel multiplexed loop interface for data transfer and control between data processing systems and subsystems 失效
    并行复用回路接口，用于数据处理系统和子系统之间的数据传输和控制

    公开(公告)号：US3919483A

    公开(公告)日：1975-11-11

    申请号：US42797073

    申请日：1973-12-26

    Applicant: IBM

    Inventor： GINDI ABRAHAM M ,  LANG DONALD J

    IPC: G06F13/38 ,  G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  H04J3/08

    CPC classification number: G06F13/362

    Abstract: A communication mechanism in which subsystems are attached in a closed loop. Communication between subsystems is accomplished by allocating time slots in both input and output directions by means of an interface controller which allocates time slots to the individual subsystems without regard to their position on the loop. Simplex frame request lines allow subsystems in the loop to request service on an individual basis. Means are provided to simultaneously allocate frames to different devices, one reading and one writing. Outgoing frames are transmitted from the control unit to the first subsystem and from the first subsystem to subsequent subsystems in parallel. The first subsystem generates an incoming frame which is transmitted to each successive subsystem in parallel and from the last subsystem back to the controller to complete the loop.

    Abstract translation: 子系统连接在闭环中的通信机制。 子系统之间的通信是通过分配时隙到各个子系统的接口控制器在输入和输出方向上分配时隙来实现的，而不考虑它们在循环上的位置。

    SELF-CLOCKING SYSTEM HAVING A VARIABLE FREQUENCY OSCILLATOR LOCKED TO LEADING EDGE OF DATA AND CLOCK
    6.
    发明专利
    SELF-CLOCKING SYSTEM HAVING A VARIABLE FREQUENCY OSCILLATOR LOCKED TO LEADING EDGE OF DATA AND CLOCK 未知

    公开(公告)号：CA951383A

    公开(公告)日：1974-07-16

    申请号：CA103749

    申请日：1971-01-27

    Applicant: IBM

    Inventor： GINDI ABRAHAM M

    IPC: G11B20/14 ,  H04L7/033 ,  H04L25/30

    Abstract: 1338309 Automatic phase control INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [31 March 1970] 21762/71 Heading H3A In an arrangement for synchronizing a clock signal with received data, a gating signal is produced for each data pulse of a predetermined value and is applied to an error signal generator together with a signal from the clock oscillator to produce an error signal which applies control pulses to the oscillator directly and via an integrator. In one embodiment, Fig. 2, the clock oscillator signal on line 10 is fed to a pulse generator 20, which provides reset pulses for a bi-stable 22 and discharge signals for capacitor C1. The capacitor C1 then charges via positive source 26 until the arrival of a logical 1 on data line 5 sets bi-stable 22 to reverse the direction of charge, or in the event of a logical 0, until the arrival of the next capacitor discharge signal. The resulting sawtooth signal on line 6 is then applied to voltage/current converters (51, 54, Fig. 4, not shown) the outputs from which are sampled by a gating signal also derived from the controlled oscillator signal to produce a pulse signal having a magnitude dependent on the phase error. This signal is then fed to an integrator, Fig. 5 (not shown), to produce a control signal for the oscillator having a large short duration component and a small long duration component. In an alternative arrangement, Fig. 3 (not shown), the sawtooth signal on line 6 is derived directly from the clock oscillator, which is a sawtooth generator.

    7.
    发明专利
    未知

    公开(公告)号：FR2311450A1

    公开(公告)日：1976-12-10

    申请号：FR7610358

    申请日：1976-04-01

    Applicant: IBM

    Inventor： GINDI ABRAHAM M ,  HONG JU-HI J ,  STELZENMULLER WILLIAM K

    IPC: H03K5/00 ,  H03M5/12 ,  H03L7/00 ,  H04J3/06 ,  H04L5/22 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40 ,  H04L25/49 ,  H04Q11/04 ,  H03K5/153

    Abstract: An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data. This feedback signal is translated into a pair of complementary signals forming inputs to the first and second amplifiers, respectively, to vary the variable gains thereof, oppositely thereby adjusting the phase of the third signal to correspond to the phase of the original pulse encoded data.

    Synchronizing appts. for byte and frame - used in loop system coupling CPU channel to bulk storage devices
    9.
    发明专利
    Synchronizing appts. for byte and frame - used in loop system coupling CPU channel to bulk storage devices 未知

    公开(公告)号：FR2360131A1

    公开(公告)日：1978-02-24

    申请号：FR7718260

    申请日：1977-06-09

    Applicant: IBM

    Inventor： GINDI ABRAHAM M ,  LANG DONALD J

    IPC: H04J3/06 ,  H04L12/42 ,  G06F13/00 ,  G06F3/04

    Abstract: The appts. synchronises frame delimited bit stream messages on a high speed lop for communication among storage system elements. The method esp. minimizes the time for attaining frame and byte synchronization among terminals attaching storage elements to the loop. The method comprises the steps synchronizing terminals downstream from a fault terminal to a first synch reference as generated by the faulty terminal and further synching the terminals upstream to a second synch pattern generated by the primary terminal responsive to the first reference. As a consequence, the system resynchs as a function of resynching of the faulty station alone.

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