11.
    发明专利
    未知

    公开(公告)号:DE69524570D1

    公开(公告)日:2002-01-24

    申请号:DE69524570

    申请日:1995-10-06

    Applicant: IBM

    Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way, involving either a subset of available functional units, or functional units dedicated to this purpose. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

    12.
    发明专利
    未知

    公开(公告)号:DE68925523T2

    公开(公告)日:1996-08-29

    申请号:DE68925523

    申请日:1989-11-08

    Applicant: IBM

    Abstract: A compiler generates compiled object code from source code of a computer program in a manner that produces efficient object code for a computer with dissimilar register spaces. The technique comprising the steps of generating code that references symbolic registers in which the register class is not distinguished, making entries in a table denoting the context in which each symbolic register occurs and constructing an equivalence tree of symbolic registers for move instructions assigned to a same equivalence class, for each equivalence class, forming the logical OR function of register usage information for all symbolic registers in the class, and for each symbolic register that appears in more than one register space context, generating new symbolic register numbers so that there is one number for each register space, and storing the numbers in said table, and if a definition point of a symbolic register is encountered and that symbolic register is used in more than one register space context, inserting code in said program to either do the same operation as is done at the definition point in each register space or move a value in the symbolic register from one space to another. The improvement achieved is in object code space and time of execution.

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