公开(公告)号：DE69209888T2

公开(公告)日：1996-10-24

申请号：DE69209888

申请日：1992-02-06

Applicant: IBM

Inventor： BERNSTEIN DAVID ,  HOPKINS MARTIN EDWARD ,  RODEH MICHAEL

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/45

Abstract: An instruction scheduler for a computer, capable of speculatively scheduling load instructions by moving certain categories of load instructions in an input instruction sequence from a source block of instructions to a target block of instructions to form an output instruction sequence, the instruction scheduler comprising: logic for selecting a data-independent load instruction as a candidate for rescheduling; logic for determining whether the base register that the load instruction makes use of and/or the contents thereof meets any one of a number of conditions; logic for moving the selected load instruction from the source block to the target block in response to determination that any one of the conditions is met.

公开(公告)号：DE3586234D1

公开(公告)日：1992-07-23

申请号：DE3586234

申请日：1985-10-11

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  WARREN JR

IPC: G06F9/45 ,  G06F9/44

公开(公告)号：DE3685339D1

公开(公告)日：1992-06-25

申请号：DE3685339

申请日：1986-01-24

Applicant: IBM

Inventor： CHAITIN GREGORY JOHN ,  HOPKINS MARTIN EDWARD ,  MARKSTEIN PETER WILLY ,  WARREN JR

IPC: G06F9/45 ,  G06F9/44

Abstract: A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

公开(公告)号：DE3582974D1

公开(公告)日：1991-07-04

申请号：DE3582974

申请日：1985-07-08

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  HOPKINS MARTIN EDWARD ,  MARKSTEIN PETER WILLY

IPC: G06F9/44 ,  G06F9/45

Abstract: A method operable within an optimizing compiler generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element "n" in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element "n" appears. The symbolic register assigned to the tuple in the table is chosen to total the result of the computation of the non-basis element; and finally, a second table is constructed so that given a symbolic register, the computation which it represents can be retrieved.

公开(公告)号：DE69524570T2

公开(公告)日：2002-08-22

申请号：DE69524570

申请日：1995-10-06

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  NAIR RAVINDRA K

IPC: G06F9/38

Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way, involving either a subset of available functional units, or functional units dedicated to this purpose. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

公开(公告)号：AT210851T

公开(公告)日：2001-12-15

申请号：AT95115748

申请日：1995-10-06

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  NAIR RAVINDRA K

IPC: G06F9/38

Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way, involving either a subset of available functional units, or functional units dedicated to this purpose. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

公开(公告)号：CA2168896A1

公开(公告)日：1996-10-14

申请号：CA2168896

申请日：1996-02-06

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  NAIR RAVINDRA K

IPC: G06F9/38 ,  G06F9/312

Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way, involving either a subset of availablefunctional units, or functional units dedicated to this purpose. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatteranalyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

公开(公告)号：DE69209888D1

公开(公告)日：1996-05-23

申请号：DE69209888

申请日：1992-02-06

Applicant: IBM

Inventor： BERNSTEIN DAVID ,  HOPKINS MARTIN EDWARD ,  RODEH MICHAEL

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/45

Abstract: An instruction scheduler for a computer, capable of speculatively scheduling load instructions by moving certain categories of load instructions in an input instruction sequence from a source block of instructions to a target block of instructions to form an output instruction sequence, the instruction scheduler comprising: logic for selecting a data-independent load instruction as a candidate for rescheduling; logic for determining whether the base register that the load instruction makes use of and/or the contents thereof meets any one of a number of conditions; logic for moving the selected load instruction from the source block to the target block in response to determination that any one of the conditions is met.

公开(公告)号：DE68925523D1

公开(公告)日：1996-03-07

申请号：DE68925523

申请日：1989-11-08

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  WARREN HENRY STANLEY

IPC: G06F9/45

Abstract: A compiler generates compiled object code from source code of a computer program in a manner that produces efficient object code for a computer with dissimilar register spaces. The technique comprising the steps of generating code that references symbolic registers in which the register class is not distinguished, making entries in a table denoting the context in which each symbolic register occurs and constructing an equivalence tree of symbolic registers for move instructions assigned to a same equivalence class, for each equivalence class, forming the logical OR function of register usage information for all symbolic registers in the class, and for each symbolic register that appears in more than one register space context, generating new symbolic register numbers so that there is one number for each register space, and storing the numbers in said table, and if a definition point of a symbolic register is encountered and that symbolic register is used in more than one register space context, inserting code in said program to either do the same operation as is done at the definition point in each register space or move a value in the symbolic register from one space to another. The improvement achieved is in object code space and time of execution.

公开(公告)号：ES2168329T3

公开(公告)日：2002-06-16

申请号：ES95115748

申请日：1995-10-06

Applicant: IBM

Inventor： HOPKINS MARTIN EDWARD ,  NAIR RAVINDRA K

IPC: G06F9/38

Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way, involving either a subset of available functional units, or functional units dedicated to this purpose. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.