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公开(公告)号：CA1092679A
公开(公告)日：1980-12-30
申请号：CA287505
申请日：1977-09-26
Applicant: IBM
Inventor： JULIUSBURGER HANS Y , WORTZMAN DONALD
Abstract: VARIABLE INCREMENT PHASE LOCKED LOOP CIRCUIT A variable increment phase locked loop circuit designed for use in a digital data communications system wherein a data input signal is synchronized with a local feedback signal by means of comparing the data input signal and the local feedback signal, and providing. frequency adjustments to the feedback signal that are proportional to the instantaneous deviation between the data input signal and the feedback signal. In one embodiment, the circuit is not responsive to deviations between the data input signal and the feedback signal that are less than a preset threshold value. The output of the circuit is useful as a stabilized system clock signal.
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公开(公告)号：CA875778A
公开(公告)日：1971-07-13
申请号：CA875778D
Applicant: IBM
Inventor： JULIUSBURGER HANS Y , STILWELL GEORGE R JR
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公开(公告)号：FR2371089A1
公开(公告)日：1978-06-09
申请号：FR7729873
申请日：1977-09-28
Applicant: IBM
Inventor： JULIUSBURGER HANS Y , WORTZMAN DONALD
Abstract: A variable increment phase locked loop circuit designed for use in a digital data communications system wherein a data input signal is synchronized with a local feedback signal by means of comparing the data input signal and the local feedback signal, and providing frequency adjustments to the feedback signal that are proportional to the instantaneous deviation between the data input signal and the feedback signal. In one embodiment, the circuit is not responsive to deviations between the data input signal and the feedback signal that are less than a preset threshold value. The output of the circuit is useful as a stabilized system clock signal.
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Patent Agency Ranking
公开(公告)号：CA791869A
公开(公告)日：1968-08-06
申请号：CA791869D
Applicant: IBM
Inventor： CHIN PAO H , ABRAMSON PAUL , JULIUSBURGER HANS Y
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公开(公告)号：CA777984A
公开(公告)日：1968-02-06
申请号：CA777984D
Applicant: IBM
Inventor： BENNETT RICHARD W , JULIUSBURGER HANS Y
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公开(公告)号：CA1007282A
公开(公告)日：1977-03-22
申请号：CA185962
申请日：1973-11-16
Applicant: IBM
Inventor： GHOUGASIAN JOHN , HART JON , JULIUSBURGER HANS Y , LOWY PAUL
Abstract: An inductive charge sensing device is disclosed in accordance with the teachings of the present invention for use with an ink jet printing system wherein ink under pressure is applied to a nozzle and ink emitted by the nozzle thereafter breaks up into a series of drops which are electrostatically charged and subsequently deflected in order to achieve controlled printing upon a recording surface moved in front of said apparatus. The charging and deflection of individual droplets is effected under control of an applied video signal. In order for the proper information to be recorded, the charging and deflection operation must be performed in precise synchronization with the ink droplet formation. As droplets are emitted from the nozzle, the charge sensor detects charges impressed on said droplets passing adjacent to but in non-impinging relationship with said sensor and a signal is developed which may be used to control an electrical or electromechanical drop forming means associated with said nozzle and ink supply.
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公开(公告)号：CA1001211A
公开(公告)日：1976-12-07
申请号：CA185952
申请日：1973-11-16
Applicant: IBM
Inventor： JULIUSBURGER HANS Y , LOWY PAUL
Abstract: 1399066 Ink-jet printers INTERNATIONAL BUSINESS MACHINES CORP 24 Oct 1973 [11 Dec 1972] 49511/73 Heading G4H An ink-jet printer incorporates logic 28, Fig. 5, for adjusting the phase relationship between drop-forming and drop charging signals in accordance with the sensed charge on a series of test drops. Test signals are derived from a clock 30, Fig. 6 (not shown), and are applied to a nozzle vibrator 12 and an electrode 14, the charge on the test drops being monitored by a sensor 16. Clock 30 comprises a ring counter which produces pulse-trains F1-F8, Fig. 2 (not shown), successively displaced by # of a period; pulse train F1 is used to drive vibrator 12. One of F1-F8 is used to control a gate 78 through which data signals pass from a generator 76 to the charging electrode 14: this pulse train is selected by gates 82 or 88 (A1-A8) during a print or a test phase respectively, the particular gate which is enabled being determined by the output of a modulo-8 counter 48 controlled by the output from sensor 16. In an initial test phase counter 48 is set to 0 and gate A1, 88 passes pulse train F1 as test charging pulses via gates 92, 42 to electrode 14, sensor 16 (which comprises a threshold device) determines whether or not the test drops have been fully enarged and sends an output to counter 48 which enables one of gates 94 or 44 so as to decrement or increment 48 (and thereby select a different pulse train). During the remainder of the initial test period the count in 48 is alternately stepped up and down by 1 according as the drops cease to be or become fully charged; at the end of this period gate 78 is enabled by the prevailing pulse train F. The possibility that the count in 48 may be wrong by a count of 1 does not matter in practice as the counter output is fed to decoders 80, 86 which select the gate A corresponding to a count of 3 less than the actual count (e.g. A2 for a count of 5) so as to produce a "broader" print phase charging pulse than is used in the test phase. Subsequent test phases, which may take place during a "carriage return" operation for example, are as above except that counter 48 is not initialized to 0.
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公开(公告)号：CA754681A
公开(公告)日：1967-03-14
申请号：CA754681D
Applicant: IBM
Inventor： DENNARD ROBERT H , JULIUSBURGER HANS Y , SIMAITIS GERVYDAS E , NAKAGAWA NORIYUKI
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