公开(公告)号：JP2010055249A

公开(公告)日：2010-03-11

申请号：JP2008217813

申请日：2008-08-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MIYAMURA TSUYOSHI ,  SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To read/write a value of a global variable speculatively and to enable rollback, in a simulation system by a computer. SOLUTION: For each global variable used in a logical process (LPn), writing of a value into a global variable is performed by writing write time and a write value thereof into a write table 1012, and reading of a value of a global variable is performed by reading of a value from the write table, and writing the time required therefor and a read value into a read table 1014. In response to writing performed into a global variable, in a simulation system, for an entry to a read table of each logical process, if an invalid entry is found in the read table by comparing entries in the write table, a doubt message is issued to a logical process related to the read table, and the logical process having received the doubt message performs necessary rollback processing. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：在计算机的仿真系统中，以推测性方式读取/写入全局变量的值并启用回滚。 解决方案：对于在逻辑进程（LPn）中使用的每个全局变量，通过将写入时间和写入值写入写入表1012来执行将值写入全局变量中，并读取值 全局变量通过从写表读取一个值，并将所需的时间和读取值写入读表1014来执行。响应于在全局变量中的写入，在模拟系统中，对于输入到 每个逻辑进程的读表，如果通过比较写表中的条目在读表中找到无效条目，则向与读表相关的逻辑进程发出疑问消息，并且接收到疑问消息的逻辑进程执行 必要的回滚处理。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010033130A

公开(公告)日：2010-02-12

申请号：JP2008191731

申请日：2008-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To efficiently simulate a system having a plurality of heterogeneous ECUs by software means. SOLUTION: Referring to an ECU emulator or each physical apparatus simulator as a logical process, each ECU emulator is speculatively emulated, and in each logical process, even if an input event is not reached, input is predicted to proceed with processing. By this speculative execution, processing is performed in advance without waiting for output of another logical process, thus improving parallelism in processes. If actual input received belatedly does not match with input for predicted speculative execution, the speculative execution ends in failure, thereby returning back to a state at the previous time, and on the basis of actual input, the processing is reexecuted. An allowable error is set for matching determination for actually received input and input at predictive speculative execution, thus enabling setting to satisfy both of accuracy and speed of simulation. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过软件手段有效地模拟具有多个异构ECU的系统。

解决方案：参考ECU仿真器或每个物理设备模拟器作为逻辑过程，每个ECU仿真器被推测式仿真，并且在每个逻辑过程中，即使没有达到输入事件，预测输入继续进行处理。 通过这种推测执行，预先执行处理，而不等待另一逻辑进程的输出，从而改进进程中的并行性。 如果迟迟收到的实际输入与预测推测执行的输入不匹配，则推测执行结束失败，从而返回到先前的状态，并且根据实际输入，重新执行处理。 设置预测推测执行时实际接收的输入和输入的匹配确定的允许误差，从而使设置能够满足模拟的精度和速度。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009059001A

公开(公告)日：2009-03-19

申请号：JP2007223143

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OHIRA REI ,  INAGAKI TATSUSHI ,  NAKAIKE TAKUYA ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: PROBLEM TO BE SOLVED: To reduce variables not to be allocated to registers, reduce transfer of value between registers, and improve efficiency in executing a program. SOLUTION: A compiler device stores interference information indicating an interference relation between variables, selects a register according to a predetermined procedure from a reference number or more of the registers so that the same register is not allocated to the set of variables having the interference relation, allocates the register to each of the respective variables, substitutes the plurality of variables allocated to the same register with new variables, merges the interference relations for each of the plurality of variables, generates an interference relation for the new variables, updates the interference information according to the interference relation, and allocates a register selected from the reference number or more of registers according to a procedure same as the predetermined procedure to each of the variables in the program that uses the new variables so that the same register is not allocated to a set of certain variables having an interference relation based on the updated interference information. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了减少不分配给寄存器的变量，减少寄存器之间的值传输，并提高执行程序的效率。 解决方案：编译器设备存储指示变量之间的干扰关系的干扰信息，根据预定过程从参考数量或更多个寄存器中选择寄存器，使得相同的寄存器不分配给具有 干扰关系，将寄存器分配给每个变量，将分配给同一寄存器的多个变量替换为新变量，合并多个变量中的每一个的干扰关系，生成新变量的干扰关系，更新 根据干扰关系的干扰信息，并且根据与预定过程相同的过程从参考数量或更多个寄存器中选择的寄存器分配给使用新变量的程序中的每个变量，使得相同的寄存器不是 分配给具有干扰关系的一组变量 基于更新的干扰信息。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002366366A

公开(公告)日：2002-12-20

申请号：JP2001161364

申请日：2001-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KOSEKI SATOSHI ,  TAKEUCHI MIKIO ,  KOMATSU HIDEAKI

IPC: G06F9/42 ,  G06F9/45

CPC classification number: G06F8/447 ,  G06F8/441 ,  G06F8/443

Abstract: PROBLEM TO BE SOLVED: To suppress the occurrence of a stack overflow or a stack underflow to prevent the execution performance of a program from being degraded by them in program code generation for a processor which has an architecture using a register stack.
SOLUTION: A compiler 10 is provided with a register allocator 11 which allocates registers to instructions in a program as the compilation object and a code generator 12 which generates object codes on the basis of the result of register allocation by the register allocator 11. The register allocator 11 allocates logical registers to instruction in the program as the compilation object and allocates the logical registers allocated to instructions in the program to physical registers so that physical registers existing at the time of calling procedures in the program as the compilation object may be allocated in order from the bottom of the register stack.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了抑制堆栈溢出或堆栈下溢的发生，以防止在具有使用寄存器堆栈的架构的处理器的程序代码生成中程序的执行性能降低。 解决方案：编译器10具有寄存器分配器11，其将寄存器分配给作为编译对象的程序中的指令;以及代码生成器12，其根据寄存器分配器11的寄存器分配结果生成对象代码。寄存器 分配器11将逻辑寄存器分配给程序中的指令作为编译对象，并将分配给程序中的指令的逻辑寄存器分配给物理寄存器，使得在作为编译对象的程序中调用过程时存在的物理寄存器可以被分配 从寄存器堆栈的底部开始。

公开(公告)号：JP2002312176A

公开(公告)日：2002-10-25

申请号：JP2001102343

申请日：2001-03-30

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F7/38 ,  G06F15/00

Abstract: PROBLEM TO BE SOLVED: To enhance efficiency in executing a program by removing redundant sign extension commands in the program. SOLUTION: This conversion program, in particular, a compiler 10 is used for converting the execution program by controlling a computer, and causes the execution program to be realized, in the computer, the function of performing analysis on sign extension commands for extending the signs of values defined in the execution program, and the function of removing prescribed sign extension commands among sign extension commands, in the execution program according to the result of the analysis.

公开(公告)号：JP2001306331A

公开(公告)日：2001-11-02

申请号：JP2000114193

申请日：2000-04-14

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  OGASAWARA TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To perform optimization with high effect to a program including an instruction in which an exception processing is possible to happen. SOLUTION: In this compiler to convert a source code of a program described in a programming language into the one in a machine language, an optimization processing executing part 12 to perform an optimization processing to an object program converted into the machine language, a pre-processing part 11 and a post-processing part 13 to perform deformation to absorb difference in the contents between a generation point of the exception processing regarding the instruction in which the exception processing is possible to happen in the object program and a place where the exception processing is performed to the object program are provided.

公开(公告)号：JP2000081983A

公开(公告)日：2000-03-21

申请号：JP37046098

申请日：1998-12-25

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  YASUE TOSHIAKI ,  KOMATSU HIDEAKI

IPC: G06F9/44 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To remove unnecessary arranged range check by collecting arranged range check information by using data flow analysis, etc., and performing move up of the check, etc. SOLUTION: C-GEN[B] is collected according to a specified condition in the reverse order of execution in respective basic blocks B (110) and information about the C- GEN[B] is stored in a storage device. And the C-GEN[B] is propagated as adding necessary correction in the order of post order traversal for priority search of depth, C-IN [B] of the respective basic blocks B (C120) is generated and information about the C-IN[B] is stored in the storage device. Finally, a check code for versioning and an execution code in respective execution states are generated in front of a loop by using the C-IN[B] (130). The check code and the execution code are stored in the storage device for execution. Thus, the arranged range check in the loop is removed.

公开(公告)号：JP2000047879A

公开(公告)日：2000-02-18

申请号：JP19032598

申请日：1998-07-06

Applicant: IBM

Inventor： YASUE TOSHIAKI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To suppress an increase in code size in a code versioning optimization process by generating a code for a part of a program in a 1st execution state and profile information used in case of transition to a 2nd execution state and generating a code for activating a code generating process in case of the transition to the 2nd execution state. SOLUTION: At the compilation, parts of the program which can be classified into at least the 1st and 2nd execution states are selected under given conditions. A check code for the classification of the execution states generated and a code for the part of the program in the 1st execution state is generated. The profile information used in case of the transition to the 2nd execution state is generated. A code for activating the code generating process needed in case of the transition to the 2nd execution state is generated. Then the profile information, etc., are further put together by using the address where the code for activation is generated as an identification number to generate a table.

公开(公告)号：JP2590045B2

公开(公告)日：1997-03-12

申请号：JP1917794

申请日：1994-02-16

Applicant: IBM JAPAN

Inventor： OOSAWA AKIRA ,  KOMATSU HIDEAKI

IPC: G06F15/16 ,  G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F15/177

公开(公告)号：JP2011096107A

公开(公告)日：2011-05-12

申请号：JP2009251044

申请日：2009-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YOSHIZAWA TAKERO ,  KOMATSU HIDEAKI ,  CANEDO ARQUIMEDES

IPC: G06F9/45

CPC classification number: G06F11/261

Abstract: PROBLEM TO BE SOLVED: To parallelize programs shown by, for example, a block diagram.
SOLUTION: In the block diagram, when outputs of functional blocks 1214 and 1216 which do not have internal states are used by a functional block A which has an internal state, the functional block A is referred to as a use block of a functional block not having the internal state. When an output of the functional block A having the internal state is used for calculation as an input of the functional block not having the internal state, the functional block A is referred to as a definition block of the functional block not having the internal state. By visiting each functional block as a node, the number of use block sets/definition block sets is calculated per functional block based on a connection relationship between the functional block having the internal state and the functional block not having the internal state, and strands 1202 to 1212 are allocated based on the number. By this, the block diagram is divided into the strands and processing is parallelized.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：并行化例如框图所示的程序。 解决方案：在框图中，当具有内部状态的功能块A使用没有内部状态的功能块1214和1216的输出时，功能块A被称为 功能块不具有内部状态。 当具有内部状态的功能块A的输出被用作不具有内部状态的功能块的输入时，功能块A被称为不具有内部状态的功能块的定义块。 通过访问每个功能块作为节点，基于具有内部状态的功能块与不具有内部状态的功能块之间的连接关系，每个功能块计算使用块集合/定义块集合的数量，并且线条1202 到1212根据号码分配。 由此，框图被划分成股线并且处理被并行化。 版权所有（C）2011，JPO＆INPIT