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公开(公告)号:CA1229423A
公开(公告)日:1987-11-17
申请号:CA481996
申请日:1985-05-21
Applicant: IBM
Inventor: LEWIS DAVID O , MCMAHON LYNN A , SCHARDT TERRY L
Abstract: LOOK-ASIDE BUFFER LRU MARKER CONTROLLER A look-aside buffer in a computer system has a memory containing at least a first type of data and a second type of data stored in a page format. The look-aside buffer is arranged to retain at least two different real addresses as resolved by the system which indicate pages containing the different types of data. One of the addresses is indicated as least recently used by a marker and such address is deleted when a further different address is resolved by the system unless the address being resolved is an address corresponding to the first type of data. In such a case, the marker is not changed such that the second type of data addresses are not deleted from the look-aside buffer as a result of resolution of a first type data page address by the system.
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公开(公告)号:CA1226962A
公开(公告)日:1987-09-15
申请号:CA481993
申请日:1985-05-21
Applicant: IBM
Inventor: JACOBS MICHAEL N , LEWIS DAVID O , THOMFORDE DALE J
Abstract: MASKED DATA FETCH AND MODIFYING DEVICE A data reading and modifying device of a computer system has a main storage for storing first data, portions of which are to be modified by various modifying data. The access speed of the main storage is slower than the speed at which the modifying data is accessed. A controller initiates fetches of first data from the main store and selects the modifying data. A register is coupled to the main storage for receiving and storing first data as it is provided from the main storage. Portions of the register are reserved for modifying data which is preferably inserted into the register before receipt of the first data as controlled by the controller. The first data received from the main storage is inserted into remaining portions of the register and insertion of, first data into portions reserved for modifying data is inhibited, such that modified data is available without a write back to the main storage location of the data to be modified.
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公开(公告)号:CA1119308A
公开(公告)日:1982-03-02
申请号:CA334988
申请日:1979-09-04
Applicant: IBM
Inventor: LEWIS DAVID O , REED JOHN W , WALLIN GARY W
Abstract: COMMAND QUEUING FOR I/O ADAPTERS In a computer system having: an addressable storage for storing instructions, data and input-output (I/O) commands; a central processing unit (CPU) which fetches and executes instructions; and channel means connecting I/O adapters to the storage and the CPU, an apparatus transfers I/O commands to the I/O adapters whereby the I/O command is either accepted immediately or is queued by the I/O adapter. A queued command is taken up by the I/O adapter when no other data transfer operation is pending. To take up a queued command, the I/O adapter initiates a fetch of the pending command by invoking a standard data-transfer-from-storage sequence. The channel means responds to the fetch initiated by the I/O adapter to send the pending command to the I/O adapter. RO9-78-020
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公开(公告)号:CA1024658A
公开(公告)日:1978-01-17
申请号:CA215258
申请日:1974-12-02
Applicant: IBM
Inventor: LEWIS DAVID O , MILLER THOMAS H , SCHMITT STEVEN A
Abstract: A computer system executes instructions for an I/O device not attached to the system. A quasi I/O attachment device is responsive to the commands for the unattached I/O device and generates an interrupt condition. The interrupt condition causes the command instructions for the unattached I/O device to be translated to command instructions for an I/O device connected to the computer system. The I/O device attached to the system performs the designated operation and generates associated I/O device status data. This associated I/O device status data is translated into I/O device status data for the unattached I/O device and thus permits a program for operating an unattached I/O device to operate instead an I/O device attached to the system which otherwise could not be operated by that program. A second embodiment performs the emulation of the unattached I/O device remotely of the central processing unit in the computer system.
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