公开(公告)号：JPH11328023A

公开(公告)日：1999-11-30

申请号：JP3150399

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method and device to process a snooping operation in a multi-processor system. SOLUTION: When a device which snoops around a system bus 122 detects an operation which requests data resident in a local memory in a certain coherency state, the device tries intervention. If this intervention is hindered by a second device which asserts retry, the device sets a flag which provides activity record information related to the intervention where a hindrance occurs. When the device asserts the intervention again and the snooped operation is retried again at the time of a following snoop hit to the same cache position, the device takes a measure to change the coherency state of a requested cache item to the final coherency state which is expected to be the result of the original operation requesting the cache item.

公开(公告)号：JPH11328017A

公开(公告)日：1999-11-30

申请号：JP6038299

申请日：1999-03-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To realize a cache directory addressing and parity check system which reduces the data storage size for cache in a data processing system. SOLUTION: The index field of an address is mapped to lower-order cache directory address lines. The other cache directory address line, namely, the highest-order line is indexed by parity of an address tag for a cache entry to be stored in a corresponding cache directory entry or a cache entry to be retrieved from the corresponding cache directory entry. Consequently, an even parity address tag is stored in a cache directory location which has '0' in the most significant index/address bit (msb), and an odd parity address tag is stored in a cache directory location which has '1' in the most significant index/address bit.

公开(公告)号：JPH11272557A

公开(公告)日：1999-10-08

申请号：JP2664399

申请日：1999-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

CPC classification number: G06F12/0815

Abstract: PROBLEM TO BE SOLVED: To avoid an unnecessary write operation to a system memory by maintaining cache coherence in a multiprocessor computer system through the use of a coherence state with tag.
SOLUTION: When a changed value is allocated to a cache line which is loaded most recently, a state with tag can be moved by crossing a cache in a horizontal direction. When a request is given for accessing to a block, related priority is given so that only a response having the highest priority is sent to a requesting processing unit. When a cache block is in a change state in one processor and a read operation is requested by the different processor, the first processor sends a change intervention response and a read processor can hold the data in a T state.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过使用具有标签的相干状态，通过维持多处理器计算机系统中的高速缓存一致性来避免对系统存储器的不必要的写入操作。 解决方案：当将更改的值分配给最近加载的高速缓存行时，可以通过在水平方向上跨越高速缓存来移动具有标签的状态。 当给出访问块的请求时，给出相关的优先级，使得只有具有最高优先级的响应被发送到请求处理单元。 当缓存块在一个处理器中处于改变状态并且由不同处理器请求读取操作时，第一处理器发送改变干预响应，并且读取处理器可以将数据保存在T状态。

公开(公告)号：JP2004326799A

公开(公告)日：2004-11-18

申请号：JP2004128842

申请日：2004-04-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CHUNG VICENTE ENRIQUE ,  JOYNER JODY BERN ,  LEWIS JERRY DON

IPC: G06F15/173 ,  G06F9/00 ,  G06F13/12 ,  G06F13/36 ,  G06F15/16

CPC classification number: G06F15/17337

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for providing a processor book of a multiprocessor used as a building block for a large-scale data processing system. SOLUTION: The processor book is generated by using two 4 way-multichip modules (MCM). First and second MCM are constructed by using regular wiring between processors. Outer buses of respective chips in first MCM are connected to buses of corresponding chips of second MCM, and additional wiring which connects them reversely in a similar way is provided. The respective processors of first MCM can substantially directly access distributed memory structure elements of next MCM, which do not have affinity, by additional wiring. The processor book is plugged in a processor rack constituted to receive a plurality of the processor books. A plurality of the processor books collectively constitute the large-scale data processing system. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JPH11328027A

公开(公告)日：1999-11-30

申请号：JP3178799

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain a cache coherence protocol which uses a tagged coherence state to increase the memory band width without immediately writing back a change value to a system memory. SOLUTION: When a tagged state is assigned to a cache line which is loaded with the change value latest, the history state related to the tagged state which is moved between caches (in the horizontal direction) can be used furthermore. This system is also applied to a multi-processor computer system having clustered processing units, and a tagged state is applied t one of cache lines in each group of caches which support different processing unit clusters. Priority levels are assigned to different cache states, and they include tagged states for response to requests which access corresponding memory blocks. Because of use of a crossbar, a tagged intermediary response is transferred to only selected caches which are affected by this intermediary response.

公开(公告)号：JPH11328025A

公开(公告)日：1999-11-30

申请号：JP3163399

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method for maintaining data coherency by determining whether or not a 1st cache should be updated according to the operation mode of the 1st cache in response to the detection of data transfer to remotely sent and including a 2nd data item. SOLUTION: A L2 cache 14 includes a cache controller 36. The cache controller 36 manages the storage and retrieval of data in a data array 34 and manages the update of a cache directory 32 in response to a signal received from a relative L1 cache and transaction snooped through an interconnection line. Then, a read request is put in an entry in a read queue 50. The cache controller 36 services the read request by supplying requested data to the relative L1 cache and then, removes the read request from the read queue 50.

公开(公告)号：JPH11328016A

公开(公告)日：1999-11-30

申请号：JP3153599

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To maintain the coherency between a data cache and an instruction cache which are separated by cleaning a designated cache entry in the data cache and instructing to invalidate the designated cache entry of the instruction cache. SOLUTION: Combined instructions are executed repeatedly for each of cache blocks included in the whole page 224 of a memory or in the plural pages of the memory to update a graphic display and a display buffer. When a mode bit 214 is set, icbi from a local processor is handled as no operation. In different kind of a system, snooped icbi is handled as the icbi even when the mode bit 214 is set. Instead of the above, the contents at a cache position (x) are copied to another position (y) and the corresponding cache position in a horizontal cache is invalidated.

公开(公告)号：JPH11272556A

公开(公告)日：1999-10-08

申请号：JP2660499

申请日：1999-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To improve a data processing by updating a first cache with valid data in response to the independent transmission of valid data by means of a second cache through a mutual connection line connecting the first and second caches.
SOLUTION: The coherence status field of the entry of an L2 cache directory is initialized when power is turned on and it shows that both data stored in a tag field and the corresponding way of a data array are invalid. An L1 cache directory entry is also initialized to an invalid state in accordance with an MESI protocol. The coherence status of a cache line stored in one of the L2 caches 14a-14n in the invalid state can be updated in accordance with both the type of a memory request given by processors 10a-10n and the response of a memory hierarchy.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过响应于通过连接第一和第二高速缓存的相互连接线的第二高速缓存来独立地发送有效数据，通过用有效数据更新第一高速缓存来改进数据处理。 解决方案：当电源打开时，初始化L2缓存目录条目的相干状态字段，并显示存储在标签字段中的数据和数据阵列的相应方式都无效。 根据MESI协议，L1缓存目录条目也被初始化为无效状态。 可以根据处理器10a-10n给出的存储器请求的类型和存储器层次的响应来更新存储在处于无效状态的L2高速缓存器14a-14n之一中的高速缓存行的一致状态。

公开(公告)号：DE69900797T2

公开(公告)日：2002-09-19

申请号：DE69900797

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.

公开(公告)号：DE69900797D1

公开(公告)日：2002-03-14

申请号：DE69900797

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.