公开(公告)号：EP2788880A4

公开(公告)日：2015-07-15

申请号：EP12856495

申请日：2012-11-16

Applicant: IBM

Inventor： DODSON JOHN STEVEN ,  GOODMAN BENJIMAN L ,  HNATKO STEVEN J ,  WRIGHT KENNETH L

IPC: G06F12/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

Abstract: Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

公开(公告)号：EP2815321A4

公开(公告)日：2015-02-25

申请号：EP13749682

申请日：2013-01-08

Applicant: IBM

Inventor： DODSON JOHN STEVEN ,  STUECHELI JEFFREY ,  BRITTAIN MARK ANDREW ,  POWELL STEPHEN ,  RETTER ERIC EUGENE

IPC: G06F12/00 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F13/1626 ,  G06F13/1689

公开(公告)号：JP2003030170A

公开(公告)日：2003-01-31

申请号：JP2002164530

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F15/177

CPC classification number: G06F12/0813

Abstract: PROBLEM TO BE SOLVED: To provide an NUMA architecture having improved queuing, storage communication efficiency. SOLUTION: A computer system includes a home node and at least one remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, and a memory controller coupled to the local interconnect and the home system memory. In response to receipt of a data request from the remote node, the memory controller transmits requested data from the home system memory to the remote node and conveys responsibility for global coherency management for the requested data from the home node to the remoter node in a separate transfer. By decoupling responsibility for global coherency management from delivery of the requested data, the memory controller queue allocated to the data request can be deallocated earlier to improve performance.

Abstract translation: 要解决的问题：提供具有改进的排队，存储通信效率的NUMA架构。 解决方案：计算机系统包括家庭节点和由节点互连耦合的至少一个远程节点。 家庭节点包括本地互连，耦合在本地互连和节点互连之间的节点控制器，家庭系统存储器以及耦合到本地互连和家用系统存储器的存储器控​​制器。 响应于从远程节点接收到数据请求，存储器控制器将所请求的数据从家庭系统存储器发送到远程节点，并且将所请求的数据的全局一致性管理的责任从单独的家庭节点传送到远程节点 转让。 通过将全局一致性管理的责任与所请求的数据的传递分离，可以更早地释放分配给数据请求的内存控制器队列，以提高性能。

公开(公告)号：JPH11328026A

公开(公告)日：1999-11-30

申请号：JP3167799

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method for maintaining the cache coherency by updating it to a 2nd state showing that a 2nd data item is effective and can be supplied in response to a request by a 1st cache. SOLUTION: A cache controller 36 puts in a read queue 50 a request to read a cache directory 32 in order to determine whether or not a designated cache line is present in a data array 34. When the cache line is present in the data array 34, the cache controller 36 puts a proper response onto an interconnection line and inserts a directory write request into a write queue 52 at need. At the directory write request, a coherency status field relating to the designated cache line is updated when the request is serviced.

公开(公告)号：JPH11272559A

公开(公告)日：1999-10-08

申请号：JP2670899

申请日：1999-02-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0811

Abstract: PROBLEM TO BE SOLVED: To improve a system for maintaining cache coherency by setting coherency indicators in the high-order level caches of a first cluster and a second cluster in a first state.
SOLUTION: A system memory 182 supplies a cache line requested in response to the read request. It is stored in an E state by an L3 cache 170a and an L2 cache 164a. The L2 cache 164a makes a shared intervention response in response to the snooping of an RWITM request, makes the requested cache line into a source and updates a coherency status indicator to an HR state. In such a case, the L3 cache 170a exclusively stores the cache line and therefore the L3 cache 170a does not generate the RWITM request on a mutual connection line 180.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过在第一状态的第一集群和第二集群的高阶级高速缓存中设置一致性指示符来改进用于维持高速缓存一致性的系统。 解决方案：系统存储器182提供响应于读取请求而请求的高速缓存行。 它由L3高速缓存170a和L2高速缓存164a存储在E状态。 响应于对RWITM请求的窥探，L2高速缓存164a进行共享干预响应，使所请求的高速缓存行进入源并将相关性状态指示符更新为HR状态。 在这种情况下，L3高速缓存170a专门存储高速缓存行，因此L3高速缓存170a不在相互连接线180上生成RWITM请求。

公开(公告)号：JPH10320283A

公开(公告)日：1998-12-04

申请号：JP10094698

申请日：1998-04-13

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  DODSON JOHN STEVEN

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide improved method and device for maintaining cache coherence in a multiprocessor/data processing system. SOLUTION: Each processor has a cache hierarchy consisting of at least a 1st level cache and a 2nd level cache. The 1st level cache is the upper level (upstream) of the 2nd level cache. Each cache includes plural cache lines. Respective cache lines are related to a state bit field to be used for identifying at least six different states including a change state, an exclusive state, a sharing state, an invalid state, a latest reading state, and an upstream undefined state. In response to the indication of a cache line including the copy of information accessed most lately, the state of the cache line is transited from the invalid state to the latest reading state. In response to the information change of the cache line of the 1st level cache without line charging operation, the state of the cache line is transited from the invalid state to the upstream undefined state.

公开(公告)号：JP2003030168A

公开(公告)日：2003-01-31

申请号：JP2002164189

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F12/08 ,  G06F15/177 ,  G06F15/16 ,  G06F15/167

CPC classification number: G06F12/0813 ,  G06F12/0817 ,  G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide an NUMA architecture having improved queuing, storage and communication efficiency.
SOLUTION: A non-uniform memory access(NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memory, and the home node contains at least a home system memory. In order to reduce access latency for data from other nodes, a portion of the remote system memory is allocated as a remote memory cache containing data corresponding to data resident in the home system memory. In one embodiment, access bandwidth to the remote memory cache is increased by distributing the remote memory cache across multiple system memories in the remote node.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供具有改进的排队，存储和通信效率的NUMA架构。 解决方案：公开了一种非均匀存储器访问（NUMA）计算机系统及其相关操作方法。 NUMA计算机系统至少包括耦合到互连的远程节点和家庭节点。 远程节点包含耦合到远程系统存储器的至少一个处理单元，并且家庭节点至少包含家用系统存储器。 为了减少来自其他节点的数据的访问延迟，远程系统存储器的一部分被分配为包含对应于驻留在家庭系统存储器中的数据的数据的远程存储器高速缓存。 在一个实施例中，通过在远程节点中的多个系统存储器上分发远程存储器高速缓存来增加对远程存储器高速缓存的访问带宽。

公开(公告)号：JPH11328015A

公开(公告)日：1999-11-30

申请号：JP3146699

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/00 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method for expelling data from a cache in a data processing system by writing the data to a system bus at the time of expelling the data and snooping them back to another cache of lower level in a cache hierarchy. SOLUTION: Data to be expelled from an L2 cache 114 are written to a system memory through a normal data path 202 to a system bus 122. Then, those data to be expelled are snooped from the system bus 122 through a snoop logical path 204 to an L3 cache 118. The expelled data can be snooped from the system bus 122 through a snoop logical path 206 to an L2 cache 116 and snooped from the system bus 122 through a snoop logical path 208 to an L3 cache 119 used to stage the data to the L2 cache 116.

公开(公告)号：JPH10326226A

公开(公告)日：1998-12-08

申请号：JP10281398

申请日：1998-04-14

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  DODSON JOHN STEVEN

IPC: G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To control a cache including a plurality of entries by substituting one alternative entry, which is different from an entry for substitution discriminated among entries, in response to a contention between a 1st and a 2nd caching operation request. SOLUTION: 1st and 2nd caching operation requests are received. Then one of entries in the cache is discriminated for substitution in response to the reception of the 2nd caching operation request. Here, if there is a contention between the 1st and 2nd caching operation requests, one alternative entry which is different from the entry for substitution is substituted in response. For example, a multiprocessor type data system 10 is equipped with more than one processors 12. Each processor 12 includes an on-board type level-1(L1) cache 14 which operates as a local storage device for instructions and data.

公开(公告)号：JPH10301908A

公开(公告)日：1998-11-13

申请号：JP9777498

申请日：1998-04-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F15/16 ,  G06F13/364 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To shorten waiting time by relating the weight of specified priority to respective plural requesters, allocating the highest present priority among plural present priorities to the priority before the plural requesters at random, and thereby approving the selected request. SOLUTION: A performance monitor 54 monitors and counts the requests or the like from the requesters 12-18. Then, at the time of receiving the requests more than the access to a shared resource 22 simultaneously approvable by a resource controller 20, the resource controller 20 relates the respective plural requesters to the respective weights of the plural priorities for indicating the possibility of allocating the highest present priority to the relating requester. Then, input from a pseudo random generator 24 is utilized, the highest priority is allocated to one of the requesters 12-18 by a practically non-critical method and the request of only the selected one of the requesters 12 18 is approved corresponding to the priority.