公开(公告)号：JP2007142430A

公开(公告)日：2007-06-07

申请号：JP2006310944

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LUO ZHIJIONG ,  LI JINGHONG ,  THOMAS W DYER

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/26506 ,  H01L21/28247

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an FET device in which an offset spacer is formed and a sidewall spacer is formed prior to a source/drain extension forming step.
SOLUTION: A gate electrode stack including a gate dielectric layer and a gate electrode thereon is formed. Diatomic nitrogen or nitrogen atoms, or both are implanted into a substrate except for a stack with a maximum energy of 10 keV or less for the diatomic nitrogen and a maximum energy of 5 keV or less for the nitrogen atoms at a temperature equal to or lower than 1,000°C for 30 minutes or less. Next, an offset spacer of oxide silicon is formed on a sidewall of the stack and a source/drain extension region is formed. A sidewall spacer of nitride is formed on the outer surface of the offset spacer. Next, a source/drain region is formed on the substrate except for the sidewall spacer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造其中形成偏移间隔物并在源极/漏极延伸形成步骤之前形成侧壁间隔物的FET器件的方法。 解决方案：形成包括栅极电介质层和栅电极的栅电极堆叠。 将双原子氮或氮原子或二者注入基底中，除了对于双原子氮具有10keV或更小的最大能量的叠层以及在等于或等于或等于等于或等于3的温度下氮原子的最大能量为5keV或更小 1000℃以上30分钟以下。 接下来，在堆叠的侧壁上形成氧化硅的偏移间隔物，形成源极/漏极延伸区域。 在偏置间隔物的外表面上形成氮化物的侧壁间隔物。 接下来，除了侧壁间隔物之外，在基板上形成源极/漏极区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2011018904A

公开(公告)日：2011-01-27

申请号：JP2010151970

申请日：2010-07-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  LIANG QINGQING ,  YIN HAIZHOU

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/417

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/7843 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor (CMOS) device that is free from causing troubles in contact formation by a stress liner, and to provide a method of manufacturing the device.SOLUTION: The complementary metal-oxide film semiconductor (CMOS) device is prepared with a constitution having a silicon-dioxide layer 102 on a silicon-substrate layer, and a concave source/drain trench. A nitride stress liner 104 is deposited in the concave source/drain trench, and further an oxide layer 106 is deposited thereon. The CMOS device is set on a handling wafer, the silicon-substrate layer is removed, and the silicon-dioxide layer 102 is etched to form an opening in contact with part of a source/drain region 170. Resultantly, a contact 180 is formed.

Abstract translation: 要解决的问题：提供一种互补的金属氧化物半导体（CMOS）器件，其不会引起应力衬垫的接触形成的麻烦，并且提供一种制造器件的方法。解决方案：互补金属氧化物膜 半导体（CMOS）器件通过在硅衬底层上具有二氧化硅层102和凹入的源/漏沟槽的结构来制备。 氮化物应力衬垫104沉积在凹形源/漏沟槽中，并且另外在其上沉积氧化物层106。 将CMOS器件设置在处理晶片上，去除硅衬底层，并且蚀刻二氧化硅层102以形成与源极/漏极区域170的一部分接触的开口。结果，形成接触件180 。

公开(公告)号：JP2008172237A

公开(公告)日：2008-07-24

申请号：JP2008001329

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  LUO ZHIJIONG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To form fully silicided dual gates on fins of a FinFET device by correctly controlling a thickness of remaining polysilicon gates using a CMP method.
SOLUTION: A method for forming a fully silicided gate on the each fin of a FinFET device includes steps of: pattern-forming a gate stack consisting of a polysilicon layer and a polysilicon germanium layer on the each fin; removing the polysilicon germanium layer on one of the fins; forming a metal layer on the each fin; and forming the fully silicided gate on the each fin of the FinFET by annealing the FinFET device.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过使用CMP方法正确地控制剩余多晶硅栅极的厚度，在FinFET器件的鳍片上形成完全硅化的双栅极。 解决方案：在FinFET器件的每个鳍上形成全硅化栅的方法包括以下步骤：在每个鳍上形成由多晶硅层和多晶硅锗层组成的栅叠层; 去除其中一个翅片上的多晶硅锗层; 在每个翅片上形成金属层; 以及通过对FinFET器件进行退火，在FinFET的每个鳍上形成完全硅化的栅极。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007251163A

公开(公告)日：2007-09-27

申请号：JP2007057115

申请日：2007-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  YANG HAINING ,  LUO ZHIJIONG

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor-on-insulator (SOI) substrate which has a patterned buried insulator layer included in differing depths. SOLUTION: The SOI substrate has a substantially planar upper surface and further includes: (1) first regions that include no buried insulator in any way; (2) second regions that include first portions of a patterned buried insulator layer 12 at a first depth (i.e., a depth measured from the planar upper surface of the SOI substrate); and (3) third regions that include second portions of the patterned buried insulator layer 12 at a second depth, wherein the first depth is deeper than the second depth. One or more field effect transistors (FETs) 20, 40 can be formed in the SOI substrate. For example, the FETs may have: channel regions in the first regions of the SOI substrate; source regions and drain regions in the second regions of the SOI substrate; and source/drain extension regions in the third regions of the SOI substrate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有不同深度的图案化掩埋绝缘体层的绝缘体上半导体（SOI）衬底。 解决方案：SOI衬底具有基本平坦的上表面，并且还包括：（1）以任何方式不包括埋入绝缘体的第一区域; （2）在第一深度（即从SOI衬底的平面上表面测量的深度）上包括图案化的掩埋绝缘体层12的第一部分的第二区域; 和（3）第三区域，其包括在第二深度处的图案化掩埋绝缘体层12的第二部分，其中第一深度比第二深度深。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）20,40。 例如，FET可以在SOI衬底的第一区域中具有：沟道区域; SOI衬底的第二区域中的源极区和漏极区; 以及SOI衬底的第三区域中的源极/漏极延伸区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007134718A

公开(公告)日：2007-05-31

申请号：JP2006303401

申请日：2006-11-08

Applicant: Chartered Semiconductor Mfg Ltd ,  Internatl Business Mach Corp ,  Samsung Electronics Co Ltd ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  サムスン エレクトロニクス カンパニー リミテッド ,  チャータード・セミコンダクター・マニュファクチャリング・リミテッド

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

IPC: H01L21/8238 ,  C23C16/34 ,  H01L21/318 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823807

Abstract: PROBLEM TO BE SOLVED: To provide a SMT (stress memory technique) for both of an nFET and a pFET.
SOLUTION: The method includes forming a tensile stress layer 120 over the nFET 104 and a compressive stress layer 122 over the pFET 106, annealing 150 to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer 122 may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include the one used in a temperature of approximately 400-1,200°C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET 106.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为nFET和pFET两者提供SMT（应力记忆技术）。 解决方案：该方法包括在nFET104上形成拉伸应力层120，在pFET 106上形成压应力层122，退火150以将应力记忆在半导体器件中并除去应力层。 压应力层122可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括在约400-1200℃的温度下使用的退火步骤。 高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET 106中。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：SG146480A1

公开(公告)日：2008-10-30

申请号：SG2007022635

申请日：2007-03-29

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHONG YUNG FU ,  LUO ZHIJIONG

Abstract: Integrated Circuit Isolation System Disclosed herein is a method of manufacturing a self-aligned inverted T- shaped isolation structure. A method of manufacturing an integrated circuit isolation system (100) includes providing a substrate (202), forming a base insulator region (702) in the substrate (202), and depositing an insulator column (1102) having a narrower width than the base insulator region (702) on the base insulator region (702).

公开(公告)号：SG190567A1

公开(公告)日：2013-06-28

申请号：SG2013030044

申请日：2007-05-17

Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM

Inventor： LUO ZHIJIONG ,  JUDSON HOLT ,  CHONG YUNG FU

Abstract: A STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOFThe present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; Wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.Fig. 2L

公开(公告)号：SG155176A1

公开(公告)日：2009-09-30

申请号：SG2009051418

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： ZHU HUILONG ,  LUO ZHIJIONG ,  CHONG YUNG FU ,  TESSIER BRIAN LEE

Abstract: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

公开(公告)号：SG137804A1

公开(公告)日：2007-12-28

申请号：SG2007036031

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： ZHU HUILONG ,  LUO ZHIJIONG ,  CHONG YUNG FU ,  TESSIER BRIAN LEE

Abstract: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material (130) over the transistor (102A, 102B) including a gate (110) thereof; removing a portion of the intrinsically stressed material (130) over the gate (110); removing at least a portion of the gate (110), allowing stress retained by the gate (110) to be transferred to the channel; replacing (or refilling) the gate (110) with a replacement gate (160); and removing the intrinsically stressed material. Removing and replacing the gate (110) allows stress retained by the original gate (110) to be transferred to the channel, with the replacement gate (160) maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

公开(公告)号：SG132607A1

公开(公告)日：2007-06-28

申请号：SG2006077119

申请日：2006-11-08

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

Abstract: A method for providing a dual stress memory technique in a semiconductor device (100) including an nFET (104, 204) and a pFET (106, 206) and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer (120) over the nFET (104) and a compressive stress layer (122) over the pFET (106), annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.