公开(公告)号：DE3476499D1

公开(公告)日：1989-03-02

申请号：DE3476499

申请日：1984-04-12

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037

Abstract: A latching circuit with reduced signal delay is disclosed comprising a latch (3') and an output logic function circuit (4'). The same signals are applied to the output gate (1') of the latch and to the logic function circuit (4'), whereby the output gate (1') and the logic function circuit (4') effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal (f) is applied only to the logic function circuit (4') but not to the latch (3'). Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.

公开(公告)号：DE2247704A1

公开(公告)日：1973-06-20

申请号：DE2247704

申请日：1972-09-28

Applicant: IBM

Inventor： HENLE ROBERT ATANASIUS ,  MALEY GERALD ADRIAN ,  PRICER WILBUR DAVID

IPC: G06F12/16 ,  G06F1/00 ,  G06F7/00 ,  G06F11/10 ,  G06F11/18 ,  G06F15/78 ,  H03H9/02 ,  G06F11/00

公开(公告)号：DE2225841A1

公开(公告)日：1973-01-04

申请号：DE2225841

申请日：1972-05-27

Applicant: IBM

Inventor： MALEY GERALD ADRIAN

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/48 ,  G11C29/00

Abstract: A memory correcting system in accordance with this disclosure is an integral part of a digital electronic computer having a monolithic memory. The memory correcting system detects, records and analyzes errors occurring during normal operation of the computer. Also, the memory correcting system systematically addresses the monolithic memory on a cycle stealing basis monitoring the general health of the monolithic memory. The systematic reading and writing of all monolithic memory locations prevents the accumulating effects of random errors. By detecting single errors as rapidly as possible, the probability of acquiring additional errors that are above the correcting capabilities of the redundancy code are avoided.