1.
    发明专利
    未知

    公开(公告)号:DE69331449D1

    公开(公告)日:2002-02-21

    申请号:DE69331449

    申请日:1993-02-12

    Applicant: IBM

    Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.

    3.
    发明专利
    未知

    公开(公告)号:DE69331449T2

    公开(公告)日:2002-09-26

    申请号:DE69331449

    申请日:1993-02-12

    Applicant: IBM

    Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.

    4.
    发明专利
    未知

    公开(公告)号:AT212136T

    公开(公告)日:2002-02-15

    申请号:AT93301037

    申请日:1993-02-12

    Applicant: IBM

    Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.

    CONFIGURABLE, RECOVERABLE PARALLEL BUS

    公开(公告)号:CA2082078C

    公开(公告)日:1996-11-19

    申请号:CA2082078

    申请日:1992-11-04

    Applicant: IBM

    Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.

    SINGLE CLOCKED LATCH CIRCUIT
    6.
    发明专利

    公开(公告)号:DE3465231D1

    公开(公告)日:1987-09-10

    申请号:DE3465231

    申请日:1984-11-14

    Applicant: IBM

    Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches (1, 2, 3). Each of two latches (1, 2) receives one set and one reset signal. The third latch (3) receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch (3) and of one of the first two latches (1, 2). A data signal is applied to the set terminal of the third latch (3). The other of the first two latches (1,2) constitutes the output latch (2) and is connected to receive the outputs of the remaining latches. The output latch (2) produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

    8.
    发明专利
    未知

    公开(公告)号:AT185222T

    公开(公告)日:1999-10-15

    申请号:AT93100833

    申请日:1993-01-21

    Applicant: IBM

    Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

    HIGH PERFORMANCE CHANNELS FOR DATA PROCESSING SYSTEMS BUS

    公开(公告)号:CA2089771C

    公开(公告)日:1996-10-01

    申请号:CA2089771

    申请日:1993-02-18

    Applicant: IBM

    Abstract: Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being canceled.

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