公开(公告)号：DE69031547D1

公开(公告)日：1997-11-13

申请号：DE69031547

申请日：1990-05-31

Applicant: IBM

Inventor： BONEVENTO FRANCIS MICHAEL ,  CHISHOLM DOUGLAS RODERICK ,  DODDS SAMMY DAVIS ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST NELSON

IPC: G06F13/12

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：DE69122937D1

公开(公告)日：1996-12-05

申请号：DE69122937

申请日：1991-07-18

Applicant: IBM

Inventor： BONEVENTO FRANCIS MICHAEL ,  MANDESE ERNEST NELSON ,  MENDELSON RICHARD NEIL

IPC: G06F13/24

Abstract: This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus. An interrupt controller is coupled to the microprocessor and bus for recognising delivery of an interrupt signal and for periodically generating an interrupt reset signal and delivering reset signals to all of the input/output devices simultaneously for setting all of the devices to a condition indicative of no request for access to said microprocessor.