公开(公告)号：DE3777797D1

公开(公告)日：1992-04-30

申请号：DE3777797

申请日：1987-01-28

Applicant: IBM

Inventor： CLOSS FELIX HUGO ,  MUELLER JOHANN RUDOLF ,  ZAFIROPULO PITRO ALOIS

IPC: H04Q11/04 ,  H04L12/56 ,  H04L12/64 ,  H04L12/54

Abstract: Switching exchange equipment interconnects communication lines (11A, 11B, 13A, 13B) carrying sync. information traffic (CS), or async. data packets (PS). The communication lines are connected to CS and output buffers (33,35) and PS input and output buffers (47,55), respectively, in the exchange. A bus arrangement interconnects all input and output buffers and has data bus lines (23) for transferring data and addresses, a CS access control line (63) for the CS input buffers and a PS access control line (65) for the PS input buffers. A first control for each CS input buffer accumulates minipackets of sync. information (CS) received on associated input lines (11A) separately for each destination output line (11B) and stores them in the respective CS input buffer. It attaches an end indicator to the last minipacket stored in the CS input buffer in each time frame period.