公开(公告)号：DE3579466D1

公开(公告)日：1990-10-04

申请号：DE3579466

申请日：1985-12-23

Applicant: IBM

Inventor： MUELLER JOHANN RUDOLF ,  ZAFIROPULO PITRO ALOIS ,  CLOSS FELIX HUGO ,  BUX WERNER KLAUS ,  VAN AS HARMEN ROELOF

IPC: H04Q11/04 ,  H04L12/433 ,  H04L12/46 ,  H04L12/64 ,  H04L12/28

Abstract: In a local area communication system comprising token rings (11) with synchronous bandwidth managers SBM (15) for issuing priority tokens for quasi-synchronous frames at regular intervals, the rings are interconnected by a time division muliplex PBX unit (31, 33) via their SBM units. Buffers are provided in each SBM for synchron­ous information blocks transferred from and to the ring, and the TDM control (31) can independently access these buffers for TDM switching of the individual bytes of said information blocks. Besides this PBK interconnection for synchronous information or voice, the rings are also interconnected by a backbone bus or ring for transfer of asynchronous data between rings. A special slot re­arrangement procedure is provided to improve the filling of time slots in the quasi-synchronous frames that are no longer used after release of a connection, to allow for addapting the frame length (number of issued slots) to the number of existing connections.

公开(公告)号：DE3777797D1

公开(公告)日：1992-04-30

申请号：DE3777797

申请日：1987-01-28

Applicant: IBM

Inventor： CLOSS FELIX HUGO ,  MUELLER JOHANN RUDOLF ,  ZAFIROPULO PITRO ALOIS

IPC: H04Q11/04 ,  H04L12/56 ,  H04L12/64 ,  H04L12/54

Abstract: Switching exchange equipment interconnects communication lines (11A, 11B, 13A, 13B) carrying sync. information traffic (CS), or async. data packets (PS). The communication lines are connected to CS and output buffers (33,35) and PS input and output buffers (47,55), respectively, in the exchange. A bus arrangement interconnects all input and output buffers and has data bus lines (23) for transferring data and addresses, a CS access control line (63) for the CS input buffers and a PS access control line (65) for the PS input buffers. A first control for each CS input buffer accumulates minipackets of sync. information (CS) received on associated input lines (11A) separately for each destination output line (11B) and stores them in the respective CS input buffer. It attaches an end indicator to the last minipacket stored in the CS input buffer in each time frame period.

公开(公告)号：GB1267625A

公开(公告)日：1972-03-22

申请号：GB1887870

申请日：1970-04-21

Applicant: IBM

Inventor： CLOSS FELIX HUGO

IPC: H04J3/00 ,  H04J3/16 ,  H04N21/2365 ,  H04N21/434

Abstract: 1,267,625. Multiplex pulse-code signalling. INTERNATIONAL BUSINESS MACHINES CORP. 21 April, 1970 [14 May, 1969], No. 18878/70. Heading H4L. A time-division multiplexing arrangement includes a selector switch receiving signals on a number of lines and providing at each slot time a signal on one line only of a corresponding number of output lines, the line selected by the switch being a pseudo-random choice from among those corresponding to " busy " input lines. As shown, inputs 1-4 if busy set flipflops 32-1 to 32-4 at the beginning of each slot period and switch 10 selects one output line 35-1 to 35-4 to gate the information pulse train through one of the gates 34 to the output 12. The end of each time slot is reserved for the coded address of the input line, and this is generated at 11 and inserted after the information bits. Selection of one output when more than one input is receiving data is effected in pseudo-random manner under control of a gated recirculating shift register 13 clocked at the time-slot rate and controlling n stages of gates in 10 (where unit 10 has 2 n inputs); the arrangement of gates is illustrated in Fig. 2a (not shown). The invention is described in relation to black-and-white picture transmission (e.g. in a system as described in Specification 1,256,631) where grey levels are digitized, possibly using a run-length coding method.