公开(公告)号：DE3382447D1

公开(公告)日：1991-12-12

申请号：DE3382447

申请日：1983-04-13

Applicant: IBM

Inventor： OLNOWICH HOWARD T

IPC: G06F12/08

Abstract: A cache memory (10) for a data processing system having a tag array (22) in which each tag word can contain a sector address (A18-A31) and represents a predetermined set or block group of consecutively addressable data block locations in a data array (26). The lower order set address bits (A8-A17) concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits (A6-A7). Each tag word read out must compare equal (28) with the high order sector bits (A18-A31) of the address and an accompanying validity bit (Vi) for each accessed block location in its group must be ON in order to effect (30) a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.

公开(公告)号：BR9101410A

公开(公告)日：1991-11-26

申请号：BR9101410

申请日：1991-04-09

Applicant: IBM

Inventor： OLNOWICH HOWARD T

IPC: G06F13/00 ,  G06F1/06 ,  G06F1/08 ,  G06F13/42

Abstract: A computer system (10) which includes a synchronous digital, multibit system bus (18) having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit (22) which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit (14) and a slave circuit (16) connected to the system bus. The master circuit (14) includes master speed indication circuitry (15) which provides a master speed indicator indicating the operating speed of the master circuit (14) to the master speed indicator path. The slave circuit (16) includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit (16) to the slave speed indicator path. The bus controller (22) provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit (14) and the slave circuit (16) may both function at the different frequency of the second clock.