公开(公告)号：DE3166951D1

公开(公告)日：1984-12-06

申请号：DE3166951

申请日：1981-07-14

Applicant: IBM

Inventor： POGGE HANS BERNHARD

IPC: H01L21/76 ,  G03F7/09 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762

Abstract: A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO2 layer, openings formed through the polycrystalline layer and SiO2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO2 layer.

公开(公告)号：DE2964728D1

公开(公告)日：1983-03-17

申请号：DE2964728

申请日：1979-09-07

Applicant: IBM

Inventor： POGGE HANS BERNHARD

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

公开(公告)号：AU5207979A

公开(公告)日：1980-05-08

申请号：AU5207979

申请日：1979-10-23

Applicant: IBM

Inventor： POGGE HANS BERNHARD

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/263 ,  H01L21/308 ,  H01L21/465

公开(公告)号：DE2805169A1

公开(公告)日：1978-08-31

申请号：DE2805169

申请日：1978-02-08

Applicant: IBM

Inventor： POGGE HANS BERNHARD

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762

Abstract: A process which utilizes an anodized porous silicon technique to form dielectric isolation on one side of a semiconductor device is described. Regions of silicon semiconductor are fully isolated from one another by this technique. The starting wafer typically is predominantly P with a P+ layer thereon. A P or N layer over the P+ layer is formed thereover such as by epitaxial growth. The surface of the silicon is oxidized and a photoresist layer applied thereto. Openings are formed in the photoresist. Openings are formed in the silicon dioxide using the photoresist as a mask and appropriate etching techniques. The openings in the silicon dioxide define the regions to be etched by reactive ion etching. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form porous silicon throughout the P+ layer. The structure is then placed in a thermal oxidation ambient until the porous silicon layer has been fully oxidized to silicon dioxide. The openings through the surface layer are filled up with oxide to fully isolate the P or N surface layer.

公开(公告)号：DE2752439A1

公开(公告)日：1978-06-08

申请号：DE2752439

申请日：1977-11-24

Applicant: IBM

Inventor： MADER SIEGFRIED ,  MASTERS BURTON JOSEPH ,  POGGE HANS BERNHARD

IPC: H01L21/265 ,  H01L29/167